1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-24MAY 2007JEDECSTANDARDDefinition of the SSTUB32865for DDR2 RDIMM Applications28-bit 1:2 Registered Buffer with Parity NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level
2、 and subsequently reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purc
3、haser in selecting and obtaining with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents o
4、r articles, materials, or processes. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to p
5、roduct specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standa
6、rd or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded
7、free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/ca
8、talog.cfm. Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering i
9、nto a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-24Page 1DEFINITION OF THE SSTUB32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS(From
10、 JEDEC Board Ballot JCB-07-14, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by
11、 4 or similar high-density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410MHz.The purpose is to provide a standard for the SSTUB32865 (see Note) logic device, for unifo
12、rmity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.NOTE The designation SSTUB32865 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific c
13、haracters to make up a complete part designation.2 Device standard2.1 DescriptionThis 28-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDDoperation.All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8
14、V CMOS drivers that have been optimized to drive the DDR2 DIMM load.The SSTUB32865 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.The device supports low-power standby operation. When the reset input (RESET) is low, the differen
15、tial input receivers are disabled, and un-driven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level
16、.To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed bet
17、ween the two. When entering reset, the register will be cleared and the data outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differenti
18、al input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTUB32865 must ensure that the outputs will remain low, thus ensuring no glitches on the output. If
19、 the data inputs are not held low, then DCS0 and DCS1 must be held high, DODT0 and DODT1, DCKE0, and DCKE1 must be held low, and all other inputs must remain stable (either low or high) for a minimum of tACT(max) after the rising edge of RESET. JEDEC Standard No. 82-24 Page 22 Device standard (contd
20、)2.1 Description (contd)The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will f
21、orce the Qn outputs low and the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEN input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs.The SSTUB32865 includes a parity checking functi
22、on. The SSTUB32865 accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs (with either DCS0 or DCS1 active) and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). If an error occurs and the PTYE
23、RR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the PTYERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a par
24、ity error occurs on the clock cycle before the device enters the low-power mode (LPM) and the PTYERR output is driven low, then it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not
25、 included in the parity check computation.The parity error output PTYERR will be reset to high by RESET transitioning low and will not be decoded until after RESET goes high and DCS0 and/or DCS1 are asserted low. CSGateEN does not affect PTYERR operation.JEDEC Standard No. 82-24Page 32 Device standa
26、rd (contd)2.2 160-ball TFBGA (MO-246A)Package options include 160-ball Thin Profile Fine Pitch BGA (TFBGA) (12 18 array, 9.0 13.0 mm body size, 0.65 mm pitch, MO-246, Issue A).Figure 1 Pinout configurationJEDEC Standard No. 82-24 Page 42 Device standard (contd)2.3 Pinout top view for 160-ball TFBGAA
27、n empty cell indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH.Figure 2 Pinout top view for 160-ball TFBGA (12 18 grid)12345678910112AVREF
28、NC PARIN NC NC QCKE1A QCKE0A Q21A Q19A Q18A Q17B Q17ABD1 D2 NC NC NC QCKE1B QCKE0B Q21B Q19B Q18B QODT0B QODT0ACD3 D4 QODT1B QODT1ADD6 D5 VDDL GND NC NC GND GND Q20B Q20AED7 D8 VDDL GND VDDL VDDR GND GND Q16B Q16AFD11 D9 VDDL GND VDDR VDDR Q1B Q1AGD18 D12 VDDL GND VDDR VDDR Q2B Q2AHCSGate END15 VDDL
29、 GND GND GND Q5B Q5AJCK DCS0 GND GND VDDR VDDR QCS0B QCS0AKCK DCS1 VDDL VDDL GND GND QCS1B QCS1ALRESET D14 GND GND VDDR VDDR Q6B Q6AMD0 D10 GND GND GND GND Q10B Q10AND17 D16 VDDL VDDL VDDR VDDR Q9B Q9APD19 D21 GND VDDL VDDL VDDR VDDR GND Q11B Q11ARD13 D20 GND VDDL VDDL GND GND GND Q15B Q15ATDODT1 DO
30、DT0 Q14B Q14AUDCKE0 DCKE1 MCL PTYERR MCH Q3B Q12B Q7B Q4B Q13B Q0B Q8BVVREF MCL MCL NC MCH Q3A Q12A Q7A Q4A Q13A Q0A Q8AJEDEC Standard No. 82-24Page 52 Device standard (contd)2.4 Terminal functionsTable 1 Terminal functionsSignal Group Signal Name Type DescriptionUngated inputs DCKE0, DCKE1, DODT0,
31、DODT1SSTL_18 DRAM function pins not associated with Chip Select.Chip Select gated inputsD0 . D21 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW.Chip Select inputsDCS0, DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes and parity checking, and as suc
32、h at least one will be low when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN high) when at least one Chip Select input is LOW. Re-driven outputsQ0A.Q21A, Q0B . Q21B, QCS0-1A,B, QCKE0-1A,B, QODT0-1A,BSSTL_18 Outputs of the register, valid
33、after the specified clock count and immediately following a rising edge of the clock.Parity input PARIN SSTL_18 Parity input for the D0 . D21 inputs; arrives one clock cycle after the corresponding data input.Parity error outputPTYERR Open drain When LOW, this output indicates that a parity error wa
34、s identified associated with a valid address and/or command input. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition).Program inputs CSGateEN 1.
35、8 V LVCMOSChip Select Gate Enable. When HIGH, the D0D21 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0.D21 inputs will be latched and re-driven on every rising edge of the clock.Clock inputs CK, CK SSTL_18 Differential mas
36、ter clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CK).Miscellaneous inputsMCL, MCH Must be connected to a logic LOW or HIGH.RESET 1.8 V LVCMOSAsynchronous reset input. When LOW, it causes a reset of the internal latches, thereby f
37、orcing the outputs LOW. RESET also resets the PTYERR signal.VREF 0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability.JEDEC Standard No. 82-24 Page 62 Device standard (contd)2.5 Function tableTable 2 Function table (each
38、 flip flop)Inputs OutputsRESET DCS0 DCS1CSGate ENCK CKDn, DODTn, DCKEnQn QCS0QCS1QODT, QCKEHLL X LLLLLHLL X HHLLHH L L X L or H L or H XQ0Q0Q0Q0HLH X LLLHLHLH X HHLHHH L H X L or H L or H XQ0Q0Q0Q0HHL X LLHLLHHL X HHHLHH H L X L or H L or H XQ0Q0Q0Q0HHH L LLHH LHHH L HHHH HH H H L L or H L or H XQ0Q
39、0Q0Q0HHHHLQ0HH LHHHHHQ0HH HH H H H L or H L or H XQ0Q0Q0Q0LX or floatingX or floatingX or floatingX or floatingX or floatingX or floatingLL L LJEDEC Standard No. 82-24Page 72 Device standard (contd)2.5 Function table (contd)Table 3 Parity and standby function tableInputs OutputRESET DCS0 DCS1 CK CK
40、of inputs = H(D0-D21)PARIN* PTYERR*HLHEven L HHLHOdd L LHLH Even H LHLHOdd H HHHLEven L HHHL Odd L LHHLEven H LHHLOdd H HHHHXXPTYERR0H X X L or H L or H X XPTYERR0LX or floatingX or floatingX or floatingX or floatingX or floatingX or floatingH* PARIN arrives one clock cycle after the data to which i
41、t applies. All D inputs must be driven to a known state for parity to be calculated correctly.* This transition assumes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR is low, it stays latched low for two clock cycles or until RESET is driven low. CSGateEN is “dont care”
42、for PTYERR. If DCS0, DCS1, and CSGEN are driven high, the device is placed in low-power mode (LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the PTYERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driv
43、en low.JEDEC Standard No. 82-24 Page 82 Device standard (contd)2.6 Logic diagramFigure 3 Logic diagram (positive logic)2222DRQVREFPARINCSGateEND0D21DRQDRQDRQDRQDRQDRQ22(CS ACTIVE)PARITYGENERATORANDCHECKERPTYERRQ0AQ0BQ21AQ21BQCS0AQCS0BQCS1AQCS1BQCKE0AQCKE0BQODT0AQODT0BQCKE1AQCKE1BQODT1AQODT1B. . . .
44、. . . . . . .DCS0DCS1DCKE0DCKE1DODT0DODT1CKCKRESETJEDEC Standard No. 82-24Page 92 Device standard (contd)2.7 Register timingFigure 4 RESET switches from L to H(1) After RESET is switched from LOW to HIGH, if DCS0 or DCS1 are held Low than all data and PAR_IN input signals must be held Low for a mini
45、mum time tACT(max.) to avoid false error. If DCS0 or DCS1 are held High than all data and PAR_IN input signals must be held at valid logic levels for a minimum time of tACT(max.) to avoid false error.)()()()()()()()()()(RESETDCSnCKCKDn(1)QnPARINPTYERRH, L, or X H or LtACTtSUtHn n+1 n+2 n+3 n+4tPDM,
46、tPDMSSCLK to QtSUtHtPHL,CLK to PTYERRtPHL, tPLHCLK to PTYERRJEDEC Standard No. 82-24 Page 102 Device standard (contd)2.7 Register timing (contd)Figure 5 RESET being held HIGHH or LtSUtHn n+1 n+2 n+3 n+4tPDM, tPDMSSCK to QtSUtH)()()()()()()()()()()()()()(Unknown inputeventOutput signal is dependent o
47、nthe prior unknown input event)()()()()()()()()()()()()()()()(DCSnRESETCKCKDn(1)QnPARINPTYERRtHL, tLHCK to PTYERRJEDEC Standard No. 82-24Page 112 Device standard (contd)2.7 Register timing (contd)Figure 6 RESET switches from H to L(1) After RESET is switched from HIGH to LOW, all data and clock inpu
48、t signals must be set and held at valid logic levels (not floating) for a minimum time of tINACT(max.).)()()()()()()()()()(RESETDCSnCKCKDn(1)QnPARINPTYERRH, L, or X H or LtINACTtPLHRESET to PTYERR)()()()()()()()()()()()()()()()()()(tPHLRESET to QJEDEC Standard No. 82-24 Page 122 Device standard (con
49、td)2.7 Register timing (contd)Figure 7 Timing diagram during start-up when data inputs are Low or High (RESET switches from L to H)After REST is switched from low to high, DCS0 and DSC1 must be held HIGH, DODT0, DODT1, DCKE0 and DCKE1 must be held LOW, and all other inputs must remain stable either LOW or HIGH (not floating) for a minimum time of tACTmax. nCKCKRESET3 nstACTn+1 n+2 n+3 n+4PTYERRDCS0DODTn,DCKEnDnPAR_INQCSnQODTn,QCKEnQnDCS1H or LH, L
