1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-29ADECEMBER 2010JEDECSTANDARD(Revision of JESD82-29, December 2009)Definition of the SSTE32882 Registering Clock Driver with Parity and Quad ChipSelects for DDR3/DDR3L/DDR3U RDIMM1.5 V/1.35 V/1.25 V ApplicationsNOTICEJEDEC standards and publications con
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10、or refer to www.jedec.org under Standards and Documents for alternative contact information.JEDEC Standard No. 82-29APage 1DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DD3/DDR3L/DDR3U RDIMM 1.5 V, 1.35 V, OR 1.25 V APPLICATIONS(From JEDEC Board Ballot JC
11、B-10-55, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets
12、 on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.NOTE The designation SSTE32882 refers to the part designation of a
13、 series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.2 Device standard2.1 DescriptionThis 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is design
14、ed for 1.5 V, 1.35 V, or 1.25 V VDDoperation.All inputs are 1.5 V, 1.35 V, or 1.25 V CMOS compatible. All outputs are 1.5 V, 1.35 V, or 1.25 V CMOS drivers optimized to drive single terminated 2550 Ohms traces in DDR3/DDR3L/DDR3U RDIMM applications. The clock outputs Yn and Yn# and control net outpu
15、ts QnCKEn, QnCSn# and QnODTn can be driven with a different strength and skew to compensate for different loading and equalize signal travel speed.The SSTE32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN#) input. When the QCSEN# input pin is open (or pulled H
16、IGH), the component has two chip select inputs, DCS0# and DCS1#, and two copies of each chip select output, QACS0#, QACS1#, QBCS0# and QBCS1#. This is the “QuadCS disabled“ mode. When the QCSEN# input pin is pulled LOW, the component has four chip select inputs DCS3:0#, and four chip select outputs,
17、 QCS3:0#. This is the “QuadCS enabled“ mode. Through the remainder of this specification, DCSn:0# will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCSn:0# will indicate all of the chip select outputs.The SSTE32882 operates from a differential c
18、lock (CK and CK#). Data are registered at the crossing of CK going HIGH, and CK# going LOW. The data could be either re-driven to the outputs once exactly one of the input signals DCSn:0# is driven LOW or it could be used to access device internal control registers when certain input conditions are
19、met. The control word mechanism is described in more detail in 2.2. Based on control register settings the device can change its output characteristics to match different DIMM net topologies. The timing can be changed to compensate for different flight time of signals within the target application.
20、By disabling unused outputs the power consumption is reduced. JEDEC Standard No. 82-29APage 22.1 Description (contd)2.1.1 InitializationThe DDR3/DDR3L/DDR3U RCD (Ultra Low Voltage) SSTE32882 can be powered-on at 1.5 V, 1.35 V, or 1.25 V. After the voltage transition, stable power is provided for a m
21、inimum of 200 uS with RESET# asserted. When the reset input RESET# is LOW, all input receivers are disabled, and can be left floating. Therefore the reference voltage (VREF) doesnt need to be stable. In addition, when RESET# is LOW, all control registers are restored to their default states. The out
22、puts QACKE0, QACKE1, QBCKE0 and QBCKE1 must drive LOW during reset. All other outputs must float. As long as the RESET# input is pulled LOW the register is in low power state and input termination is not present. A certain period of time (tACT) before the RESET# input is pulled HIGH the reference vo
23、ltage needs to be stable within specification, the clock input signal must be stable, the register inputs DCSn:0# must be pulled HIGH to prevent accidental access to the control registers and DCKE0 as well as DCKE1 must be pulled LOW. After reset and after the stabilization time (tSTAB) the register
24、 must meet the input setup- and hold specification, as well as accept and transfer input signals to the corresponding outputs. The RESET# input must always be held at a valid logic level once the input clock is present.To ensure defined outputs from the register before a stable clock has been suppli
25、ed, the register must enter the reset state during power-up. It may leave this state only after a LOW to HIGH transition on RESET# while a stable clock signal is present on CK and CK#. In the DDR3 RDIMM application, RESET# is specified to be completely asynchronous with respect to CK and CK#. Theref
26、ore, no timing relationship can be guaranteed between the two.Figure 1 Timing of clock and data during initialization sequence(1)CK# is left out for better visibility(2)DCKE0, DCKE1, DODT0, DODT1, DCS0# and DCS1# are not included in this range(3)QxCKEn, QxODTn, QxCSn# are not included in this range.
27、(4)n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled modeCK(1)VDDDCKE0:1RESET#DA/C(2)DODT0:1DCS0#DCSn:1#(4)PLL lock 6 stACT= 8 cyclestINIT= 200 sController guarantees high logicController guarantees high logicController guarantees valid logicController guarantees low logicController guarantee
28、s valid logicRegister proper function and timing starting from hereRegister drives CKE LOW until ready to transfer input signalsQxCKE0:1QxODT0:1QxCSn:0#(4)ERROUT#Step 0,1 Step 2 Step 3 Step 5 Step 6 Step 7Step 4QxA/C(3)High or LowY0:3(1)Register guarantees low logicRegister guarantees high logicJEDE
29、C Standard No. 82-29APage 32.1 Description (contd)2.1.1 Initialization (contd)From a device perspective, the initialization sequence must be as shown in Table 1.As part of the initialization all control words are reset to their default state which is “0”, except for RC6 and RC7, which are vendor-def
30、ined. After initialization, the memory controller does only need to write to those control registers whose contents need to be changed.2.1.1.1 Reset Initialization with Stable PowerThe timing diagram in Figure 1 depicts the initialization sequence with stable power and clock. This will apply to the
31、situation when we have a soft reset in the system. RESET# will be asserted for minimum 100ns. This RESET# timing is based on DDR3 DRAM Reset Initialization with Stable Power requirement, and is a minimum requirement. Actual RESET# timing can vary base on specific system requirement, but it cannot be
32、 less than 100ns as required by JESD79-3.Table 1 SSTE32882 Device Initialization Sequenceaa. X = Logic LOW or logic HIGH. Z = floating.Step Power Inputs: Signals provided by the controller Outputs: Signals provided by the deviceVDD, AVDD, PVDDRESET# Vref DCS#n:02DODT0:1DCKE0:1DA/C PAR_IN CKCK#QCS#n:
33、0bb. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled modeQODT0:1QCKE0:1QxA/C ERROUT#Y0:3Y#0:3FBOUTcc. The feedback clock (FBOUT and FBOUT#) pins may or may not be actively driven by the device.0 0V X or Z X or Z X or Z X or Z X or Z X or Z X or Z X or Z Z Z Z Z Z Z Z1 0VDDX or Z X or Z X or
34、 Z X or Z X or Z X or Z X or Z LX or ZX or ZX or ZX or Z X or Z X or Z X or Z2dd. The system may power up using either 1.5 V, 1.35 V or 1.25 V. The BIOS reads the SPD andadjusts the voltage if needed. Stable power is provided for a minimum of 200 uS with RESET#asserted.VDD1.5 V1.35 V1.35 V1.5 VL X o
35、r Z X or Z X or Z X or Z X or Z X or Z L Z ZLee. QxCKEn and ERROUT# will be driven to these logic states by the register after RESET# is driven LOW and VDD is 1.5 V, 1.35 V or1.25 V (nominal).ZH5 ZZ3 VDDL X or Z X or Z X or Z X or Z X or Z X or Z runningZZLZHZ Z4 VDDL X or Z H X or Z L X or Z X or Z
36、 running ZZLZHZ Z5 VDDLstable voltageHXLXXrunning ZZLZHZ Z6 VDDHstable voltageHXLXXrunning HLff. This indicates the state of QxODTx after RESET# switches from LOW-to-HIGH and before the rising CK edge (falling CK# edge).After the first rising CK edge, within (tSTAB- tACT) us, the state of QxODTx is
37、a function of DODTx (HIGH or LOW).LXHrunning running7gg. Step 7 is a typical usage example and is not a register requirement.VDDHstable voltageH X X X X runningAfter Step 6 (Step 7 and beyond), the device outputs are as defined in the device Function Tables (see Table 12, Table 14 and Table 16).JEDE
38、C Standard No. 82-29APage 42.1.1.1 Reset Initialization with Stable Power (contd)Figure 2 Timing of clock and data during initialization sequence with stable power(1)CK# left out for better visibility(2)DCKE0, DCKE1, DODT0, DODT1, DCS0# and DCS1# are not included in this range(3)QxCKEn, QxODTn, QxCS
39、n# are not included in this range.(4)n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.Table 2 SSTE32882 Device Initialization Sequenceawhen Power and Clock are Stablea. X = Logic LOW or logic HIGH. Z = floating.Step Power Inputs: Signals provided by the controller Outputs: Signals provi
40、ded by the deviceVDD, AVDD, PVDDRESET# Vref DCS#n:1bb. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled modeDODT0:1DCKE0:1DA/C PAR_IN CKCK#QCS#0:1QODT0:1QCKE0:1QxA/C ERROUT#Y0:3Y#0:3FBOUTcc. The feedback clock (FBOUT and FBOUT#) pins may or may not be actively driven by the device.0 VDD Hsta
41、ble voltageX X X X X running X X X X X running running1 VDD Hstable voltageX X X X X running X X X X X running running2 VDD Lstable voltageX X X X X running Z ZLdd. QxCKEn and ERROUT# will be driven to these logic states by the register after RESET# is driven LOW and VDDis nominal.ZH4ZZ3 VDD Lstable
42、 voltageX X X X X runningZZLZHZZ4 VDD Lstable voltageH X L X X running ZZLZHZZ5 VDD Lstable voltageHXLXXrunning ZZLZHZZ6 VDD Hstable voltageHXLXXrunning HLee. This indicates the state of QxODTx after RESET# switches from LOW-to-HIGH and before the rising CK edge (falling CK# edge). After the firstri
43、sing CK edge, within (tSTAB- tACT) us, the state of QxODTx is a function of DODTx (HIGH or LOW).LXHrunning running7 VDD Hstable voltageH X X X X runningAfter Step 6 (Step 7 and beyond), the device outputs are as defined in the device Function Tables (see Table 12, Table 14 and Table 16).CK(1)VDDDCKE
44、0:1RESET#DA/C(2)DODT0:1DCS0#DCSn:1#PLL lock 6 stACT= 8 cyclestINIT_Power_Stable= 100 nS Controller guarantees high logicController guarantees highh logicController guarantees low logicController guarantees valid logicRegister proper function and timing starting from hereRegister drives CKE LOW until
45、 ready to transfer input signalsQxCKE0:1QxCS0:1#ERROUT#Step 0,1 Step 2 Step 3 Step 5 Step 6 Step 7Register guarantees high logicStep 4Register guarantees low logicH or LH or LHi-ZY0:3(1)QxA/C(3)Controller guarantees valid logicH or LH or LQxODT0:1Hi-ZH or LH or LH or LH or LHigh or LowJEDEC Standard
46、 No. 82-29APage 52.1.2 ParityThe SSTE32882 includes a parity checking function. The SSTE32882 accepts a parity bit from the memory controller at its input pin PAR_IN one cycle after the corresponding data input, compares it with the data received on the D-inputs and indicates on its open-drain ERROU
47、T# pin (active LOW) whether a parity error has occurred. The computation only takes place for data which is qualified by at least one of the DCSn:0# signals being LOW.If an error occurs, and ERROUT# is driven LOW with the third input clock edge after the corresponding data on the D-inputs. It become
48、s high impedance with the 5th input clock cycle after the data corresponding with a parity error. In case of consecutive errors ERROUT# becomes high impedance with the 5th input clock cycle after the last data corresponding with a parity error. The DIMM-dependent signals (DCKE0, DCKE1, DCS0#, DCS1#,
49、 DODT0 and DODT1) are not included in the parity check computations.2.1.2.1 Parity Timing Scheme WaveformsThe PAR_IN signal arrives one input clock cycle after the corresponding data input signals. ERROUT# is generated three input clock cycles after the corresponding data is registered. If ERROUT# goes LOW, it stays LOW for a minimum of two input clock cycles or until RESET# is driven LOW. Figure 3 shows the parity diagram with single parity-error occurrence and assumes the occurrence of only one
