1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-9BMAY 2007JEDECSTANDARDDefinition of the SSTU32865 Registered Buffer with Parity for2R 4 DDR2 RDIMM Applications(Revision of JESD82-9A, November 2004)NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved
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5、epresents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relative to t
6、he content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 T
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9、er of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-9BPage 1DEFINITION OF THE SSTU32865 REGISTERED BUFFER WITH PARITYFOR 2R 4 DDR2
10、RDIMM APPLICATIONS(From JEDEC Board Ballot JCB-03-41, JCB-04-79, and JCB-07-12, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU3
11、2865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications.The purpose is to provide a standard for the SSTU32865 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.NOTE The
12、 designation SSTU32865 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.2 Device standard2.1 DescriptionThis 28-bit 1:2 registered buffe
13、r with parity is designed for 1.7 V to 1.9 V VDDoperation.All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load.The SSTU32865 operates from a differential cl
14、ock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are all
15、owed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level.To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low
16、 state during power up.In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relativ
17、e to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high tra
18、nsition of RESET until the input receivers are fully enabled, the design of the SSTU32865 must ensure that the outputs will remain low, thus ensuring no glitches on the output. If the data inputs are not held low, then DCS0 and DCS1 must be held high, DODT0 and DODT1, DCKE0, and DCKE1 must be held l
19、ow, and all other inputs must remain stable (either low or high) for a minimum of tACT(max) after the rising edge of RESET.JEDEC Standard No. 82-9BPage 22 Device standard (contd)2.1 Description (contd)The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states whe
20、n both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEnable
21、input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs.The SSTU32865 includes a parity checking function. The SSTU32865 accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data rece
22、ived on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).The parity error output PTYERR will be reset to high by RESET transitioning low and will not be decoded until after RESET goes high and DCS0 and/or DCS1 are asserted low. CSGateEN does no
23、t affect PTYERR operation.Package options include 160-ball Thin Profile Fine Pitch BGA (TFBGA) (12 18 array, 9.0 13.0 mm body size, 0.65 mm pitch, MO-246, Issue A).2.2 160-ball TFBGA (MO-246A)Figure 1 Pinout configurationJEDEC Standard No. 82-9BPage 32 Device standard (contd)2.3 Pinout top view for
24、160-ball TFBGAAn empty cell indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH.Figure 2 Pinout top view for 160-ball TFBGA (12 18 grid)12345
25、678910112AVREF NC PARIN NC NC QCKE1A QCKE0A Q21A Q19A Q18A Q17B Q17ABD1 D2 NC NC NC QCKE1B QCKE0B Q21B Q19B Q18B QODT0B QODT0ACD3 D4 QODT1B QODT1ADD6 D5 VDDL GND NC NC GND GND Q20B Q20AED7 D8 VDDL GND VDDL VDDR GND GND Q16B Q16AFD11 D9 VDDL GND VDDR VDDR Q1B Q1AGD18 D12 VDDL GND VDDR VDDR Q2B Q2AHCS
26、Gate END15 VDDL GND GND GND Q5B Q5AJCK DCS0 GND GND VDDR VDDR QCS0B QCS0AKCK DCS1 VDDL VDDL GND GND QCS1B QCS1ALRESET D14 GND GND VDDR VDDR Q6B Q6AMD0 D10 GND GND GND GND Q10B Q10AND17 D16 VDDL VDDL VDDR VDDR Q9B Q9APD19 D21 GND VDDL VDDL VDDR VDDR GND Q11B Q11ARD13 D20 GND VDDL VDDL GND GND GND Q15
27、B Q15ATDODT1 DODT0 Q14B Q14BUDCKE0 DCKE1 MCL PTYERR MCH Q3B Q12B Q7B Q4B Q13B Q0B Q8BVVREF MCL MCL NC MCH Q3A Q12A Q7A Q4A Q13A Q0A Q8AJEDEC Standard No. 82-9BPage 42 Device standard (contd)2.4 Terminal functionsTable 1 Terminal functionsSignal Group Signal Name Type DescriptionUngated inputs DCKE0,
28、 DCKE1, DODT0, DODT1SSTL_18 DRAM function pins not associated with Chip Select.Chip Select gated inputsD0 . D21 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW.Chip Select inputsDCS0, DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at
29、least one will be low when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN high) when at least one Chip Select input is LOW. Re-driven outputsQ0A.Q21A, Q0B . Q21B, QCS0-1A,B, QCKE0-1A,B, QODT0-1A,BSSTL_18 Outputs of the register, valid after
30、 the specified clock count and immediately following a rising edge of the clock.Parity input PARIN SSTL_18 Input parity is received on pin PARIN and should maintain odd parity across the D0.D21 inputs, at the rising edge of the clock.Parity error outputPTYERR Open drain When LOW, this output indicat
31、es that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition).Prog
32、ram inputs CSGateEN 1.8 V LVCMOSChip Select Gate Enable. When HIGH, the D0D21 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0.D21 inputs will be latched and redriven on every rising edge of the clock.Clock inputs CK, CK SST
33、L_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CK).Miscellaneous inputsMCL, MCH Must be connectedd to a logic LOW or HIGH.RESET 1.8 V LVCMOSAsynchronous reset input. When LOW, it causes a reset of the inter
34、nal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal.VREF 0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability.JEDEC Standard No. 82-9BPage 52 Device standard (contd)2.5 Function tableTable 2
35、 Function table (each flip flop)Inputs OutputsRESET DCS0 DCS1CSGate EnableCK CKDn, DODTn, DCKEnQn QCSQODT, QCKEHLLXLLLLHLLXHHLHH L L X L or H L or H XQ0Q0Q0HLHXLLLLHLHXHHLHH L H X L or H L or H XQ0Q0Q0HHLXLLHLHHLXHHHHH H L X L or H L or H XQ0Q0Q0HHHLLLHLHHHLHHHHH H H L L or H L or H XQ0Q0Q0HHHHLQ0HL
36、HHHHHQ0HHHHHHL or HL or HXQ0Q0Q0LX or floatingX or floatingX or floatingX or floatingX or floatingX or floatingLLLJEDEC Standard No. 82-9BPage 62 Device standard (contd)2.5 Function table (contd)Table 3 Parity and standby function tableInputs OutputRESET DCS0 DCS1 CK CK of inputs = H(D0-D21)PARIN* P
37、TYERR*HLHEven L HHLHOdd L LHLH Even H LHLHOdd H HHHLEven L HHHL Odd L LHHLEven H LHHLOdd H HHHHXXPTYERR0H X X L or H L or H X XPTYERR0LX or floatingX or floatingX or floatingX or floatingX or floatingX or floatingH* PARIN arrives one clock cycle after the data to which it applies.* This transition a
38、ssumes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR is low, it stays latched low for two clock cycles or until RESET is driven low. If DCS0, DCS1, and CSGEN are driven high, the device is placed in low-power mode (LPM). If a parity error occurs on the clock cycle befor
39、e the device enters the LPM and the PTYERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low.JEDEC Standard No. 82-9BPage 72 Device standard (contd)2.6 Logic diagramFigure 3 Logic diagram (positive logic)DQRDQRDQRDQRDQRDQRDQRPARIND0D21
40、VREF(CS ACTIVE) DCS0DCS1DCKE0,DCKE1DODT0,DODT1CSGateENRESETCKCK22PARITYGENERATORANDCHECKERQ0AQ0BQ21AQ21BQCS0AQCS0BQCS1AQCS1BQCKE0A,QCKE1AQCKE0B,QCKE1BQODT0A,QODT1AQODT0B,QODT1BPTYERR2222002aaa386JEDEC Standard No. 82-9BPage 82 Device standard (contd)2.7 Register timingFigure 4 Timing of clock, data
41、and parity signalsCKCKn - 1 n n + 1 n + 2 n + 3 n + 4 n + 5DnPARINQnPTYERRtPDMtPDMtPDMSStsuthtsuth002aaa387tPDHJEDEC Standard No. 82-9BPage 92.7 Register timing (contd)Figure 5 Timing diagram during start-up when data inputs are Low or High (RESET switches from L to H)After REST is switched from low
42、 to high, DCS0 and DSC1 must be held HIGH, DODT0, DODT1, DCKE0 and DCKE1 must be held LOW, and all other inputs must remain stable either LOW or HIGH (not floating) for a minimum time of tACTmax. nCKCKRESET3 nstACTn+1 n+2 n+3 n+4PTYERRDCS0DODTn,DCKEnDnPAR_INQCSnQODTn,QCKEnQnDCS1H or LH, L or XJEDEC
43、Standard No. 82-9BPage 102 Device standard (contd)Figure 6 Data error occurs at (n-1), LPM occurs at (n)2.8 Parity logic diagramFigure 7 Parity logic diagramn-1 n n+1 n+2 m m+1 m+2()()()()()()()()()()()()Low Power Mode (LPM)CKData ErrorPARINDCSnPTYERR()()CSGateEND22DD LATCHING AND RESET FUNCTIONsee
44、Note (1)PTYERRDQnAQnBDnPARINCLOCKQ002aaa41722(1) This function holds the error for two cycles. See functional description and timing diagram.JEDEC Standard No. 82-9BPage 112 Device standard (contd)2.9 Absolute maximum ratingsNOTE 1 Stresses beyond those listed under “absolute maximum ratings” may ca
45、use permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect dev
46、ice reliability. NOTE 2 The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.Table 4 Absolute maximum ratings over operating free-air temperature range (see Note 1)Symbol Parameter Conditions Min Max UnitVDDSupply voltage 0.5 +2.5 V
47、VIReceiver input voltage (see Note 2) 0.5 +2.5 VVODriver output voltage (see Note 2) 0.5 VDD+0.5 VIIKInput clamp current VIVDD- 50 mAIOKOutput clamp current VOVDD- 50 mAIOContinuous output current 0 VO VDD- 50 mAICCCContinuous current through each VDDor GND pin - 100 mATstgStorage temperature 65 +15
48、0 CJEDEC Standard No. 82-9BPage 122 Device standard (contd)2.10 Recommended operating conditionsNOTE The RESET input of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW.Table 5 Recommended oper
49、ating conditions (see Note)Symbol Parameter Conditions Min Nom Max UnitVDDSupply voltage 1.7 - 1.9 VVREFReference voltage 0.49 VDD0.50 VDD0.51 VDDVVTTTermination voltage VREF 40 mV VREFVREF+ 40 mV VVIInput voltage 0-VDDVVIHAC HIGH-level input voltage Data inputs VREF+ 250 mV -VILAC LOW-level input voltage Data inputs -VREF 250 mV VVIHDC HIGH-level input voltage Data inputs VREF+ 125 mV -VILDC LOW-level input voltage Data inputs -VREF 125 mV VVIHHIGH-level inp
