1、 IEC 60191-6Edition 3.0 2009-11INTERNATIONAL STANDARD NORME INTERNATIONALEMechanical standardization of semiconductor devices Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Normalisation mcanique des dispositifs semi-conducteurs Partie
2、6: Rgles gnrales pour la prparation des dessins dencombrement des botiers pour dispositifs semi-conducteurs pour montage en surface IEC60191-6:2009 THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2009 IEC, Geneva, Switzerland All rights reserved. Unless otherwise specified, no part of this publica
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17、ONALEMechanical standardization of semiconductor devices Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Normalisation mcanique des dispositifs semi-conducteurs Partie 6: Rgles gnrales pour la prparation des dessins dencombrement des bot
18、iers pour dispositifs semi-conducteurs pour montage en surface INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE WICS 31.080.01 PRICE CODECODE PRIXISBN 2-8318-1069-6 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission
19、 Electrotechnique Internationale 2 60191-6 IEC:2009 CONTENTS FOREWORD.4 1 Scope.6 2 Normative references .6 3 Terms and definitions .6 4 Design rules .7 5 Dimensions to be specified.8 6 Notes .8 Annex A (informative) Illustration of the rules.12 Annex B (informative) Optional table format.36 Bibliog
20、raphy38 Figure A.1 Illustrations of terminal projection zone.13 Figure A.2 Isometric view of an example of gauge .13 Figure A.3a Top view .14 Figure A.3b Side view 14 Figure A.3c Lead section .14 Figure A.3d Lead side view14 Figure A.4 Pattern of terminal position areas .14 Figure A.5a Top view .17
21、Figure A.5b Side view 17 Figure A.5c Lead section .17 Figure A.5d Lead side view17 Figure A.6 Pattern of terminal position areas .17 Figure A.7a Top view .20 Figure A.7b Side view 20 Figure A.7c Lead section .20 Figure A.7d Lead side view20 Figure A.8 Pattern of terminal position areas .20 Figure A.
22、9a Top view .23 Figure A.9b Side view 23 Figure A.9c Side view 23 Figure A.9d Lead shape.23 Figure A.9e Lead side view23 Figure A.9f Lead section 23 Figure A.10 Pattern of terminal position areas .23 Figure A.11a Top view .26 Figure A.11b Side view 26 Figure A.11c Side view 26 Figure A.11d Lead sect
23、ion .27 Figure A.11e Lead shape .27 Figure A.11f Lead side view.27 60191-6 IEC:2009 3 Figure A.12 Pattern of terminal position areas .27 Figure A.13a Top View.30 Figure A.13b Side View30 Figure A.13c Bottom view 30 Figure A.14 Pattern of terminal position areas .30 Figure A.15a Top view .33 Figure A
24、.15b Side view 33 Figure A.15c Bottom view 33 Figure A.16 Pattern of terminal position areas .33 Table 1 Dimensions to be specified for Group 1 .9 Table 2 Dimensions to be specified for Group 2 .10 4 60191-6 IEC:2009 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ MECHANICAL STANDARDIZATION OF SEMICONDU
25、CTOR DEVICES Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC Nationa
26、l Committees). The object of IEC is to promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly
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35、erenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. Inte
36、rnational Standard IEC 60191-6 has been prepared by subcommittee 47D: Mechanical standardization of semiconductor devices, of IEC technical committee 47: Semiconductor devices. This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004 and constitutes a technical re
37、vision. This edition includes the following significant changes with respect to the previous edition: a) scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8; b) editorial modifications on several pages; and c) technical revision to
38、ball grid array package (BGA) especially its geometrical drawing format. (two types of BGA would unify as one type as a result of revising drawing format.) 60191-6 IEC:2009 5 The text of this standard is based on the following documents: CDV Report on voting 47D/736/CDV 47D/749/RVC Full information
39、on the voting for the approval of this standard can be found in the report on voting indicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all parts of IEC 60191 series under the general title Mechanical standardization of semico
40、nductor devices can be found on the IEC website. The committee has decided that the contents of this amendment and the base publication will remain unchanged until the maintenance result date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific publication.
41、 At this date, the publication will be reconfirmed; withdrawn; replaced by a revised edition, or amended. 6 60191-6 IEC:2009 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages 1 Scope This
42、 part of IEC 60191 gives general rules for the preparation of outline drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits
43、classified as form E in Clause 3 of IEC 60191-4. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including an
44、y amendments) applies. IEC 60191-1:2007, Mechanical standardization of semiconductor devices Part 1: General rules for the preparation of outline drawings of discrete devices IEC 60191-4:2002, Mechanical standardization of semiconductor devices Part 4: Coding system and classification into forms of
45、package outlines for semiconductor device packages ISO 1101:2004 Geometrical Product Specifications (GPS) Geometrical tolerancing Tolerances of form, orientation, location and run-out 3 Terms and definitions For the purposes of this document, the following terms and definitions apply. 3.1 seating pl
46、ane plane which designates the plane of contact of the package, including any stand-off, with the surface on which it will be mounted NOTE This plane is often used as the reference plane. 3.2 reference plane plane parallel to the seating plane at a distance A3 above seating plane (does not apply to
47、leadless package) NOTE 1 The distance A3 is known as the reference plane distance. It determines the terminal projection zone (see Figure 1). NOTE 2 This distance is a theoretical dimension which is not related to any feature of the package. Its value is chosen for each package so the length of term
48、inal projection zone Lpis a good approximation of the terminal length used for mounting, e.g. the length of the part of the terminal that is soldered to the substrate. 60191-6 IEC:2009 7 3.3 terminal position area maximum area on the seating plane within which the terminal projection zone is located
49、, taking into account the maximum values of Lpand bp NOTE 1 The surface of the terminal position area is equal to l1 b3with, generally l1= Lpmax. + (HDmax. HDmin.)/2 = Lpmax. + (HEmax. HEmin.)/2 and b3 = bpmax. + x NOTE 2 Checking can be carried out by means of an appropriate gauge (see Figure 2) 3.4 pattern of ter
