1、INTERNATIONAL STANDARD lSO/IEC 10857 ANSI/IEEE Std 896.1 First edition 1994-04-27 Information technology - Microprocessor systems - Futurebus+ - Logical protocol specification Technologies de Iinformation - Systkmes 2 microprocesseurs - F that is, they are governed by a pure cause-and-effect relatio
2、nship. This is what gives this International Standard its technology-independent nature. The compelled signaling provides a designer with a logical simplicity for what takes place in the pro- tocols. As a result, there will be maximum compatibility between products designed to this International Sta
3、ndard throughout its operational lifetime. With any bus, there is the dilemma of how much the standard should specify. There must be a balance between ensuring that all boards designed by a variety of manufacturers can operate together, while not restricting the users of the bus to any preconceived
4、system design. Although the scope of this International Standard has been restricted to exclude many of the system requirements associated with bus-based com- puter systems, these are being addressed in companion standards. The common control and register interface to this series of standards for th
5、e Futurebus+, and to other pro- posed IEEE standards (in particular, IEEE Std 1596-1992 B12, IEEE P1014.1 B2, and IEEE The numbers in brackets correspond to those of the bibliography in annex A. Copyright International Organization for Standardization Provided by IHS under license with ISONot for Re
6、saleNo reproduction or networking permitted without license from IHS-,-,-ISOllEC 10857 : 1994 (E) ANSI/IEEE Std 896.1, 1994 Edition MICROPROCESSOR SYSTEMS- P1394 Bll), is embodied in the unified CSR architecture standard, IEEE Std 1212-1991 B7, along with a unified DMA architecture for moving data a
7、round a system without the need to pass through a processor (IEEE Std 1212.1-1993 B8). This set of protocols has been designed to be as close to technology-independent as possible while maintain- ing a very high level of efficiency and performance. The bus signals may be implemented using any techno
8、l- ogy (TTL, Backplane Transceiver Logic, ECL, CMOS, GaAs, etc.) so long as the Futurebus+ signaling conditions are met (incident wave switching on the transmission-line signaling environment, along with the constraints on skew, crosstalk, and transmission reliability). However, in the interest of m
9、aximum compati- bility between product families, implementations are expected to be associated with one or more IEEE Futurebus+ profiles, which specify the physical layer and set of transactions to suit a particular family of applications. Connection to Supercomputer (liOProcessorl VOProcessor P SCS
10、I 2 / IPI Disk Farm Figure l-Interfaces in a family of typical Futurebus+ systems 2 Copyright International Organization for Standardization Provided by IHS under license with ISONot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ISO/IEC 10857 : 1994 (E) FUTUREBUS+ -L
11、OGICAL PROTOCOL SPECIFICATION ANSI/IEEE Std 896.1, 1994 Edition 1.2 Normative references The following standards contain provisions which, through references in this text, constitute provisions of this International Standard. At the time of publication, the editions indicated were valid. All standar
12、ds are subject to revision, and parties to agreements based on this International Standard are encouraged to investi- gate the possibility of applying the most recent edition of the standards listed below. Members of IEC and IS0 maintain registers of currently valid International Standards. IEEE Std
13、 896.2-1991, IEEE Standard for Futurebus+ - Physical Layer and Profile Specifications.2 IEEE Std 896.3-1993, IEEE Recommended Practices for Futurebus+. * IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331
14、, USA. 3As this standard goes to press, IEEE Std 896.3-1993 is not yet published. It is, however, available in manuscript form from IEEE. Anticipated publication date is May 1994. 3 Copyright International Organization for Standardization Provided by IHS under license with ISONot for ResaleNo reprod
15、uction or networking permitted without license from IHS-,-,-ISO/IEC 10857 : 1994 (E) ANSI/IEEE Std 896.1, 1994 Edition MICROPROCESSOR SYSTEMS- 2. Definitions and structure 2.1 Special word usage 2.1.1 may: A keyword indicating flexibility of choice with no implied preference. 2.1.2 shall: A keyword
16、indicating a mandatory requirement. Designers must implement all such mandatory requirements to ensure interoperability of ISO/IEC 10857 conformant products and claim conformance to this International Standard. 2.1.3 should: A keyword indicating flexibility of choice with a strongly preferred implem
17、entation. The phrase it is recommended is used interchangeably with the keyword should. 2.2 Definitions 2.2.1 activate: a) The action of applying a set of signals to a group of bus lines. b) The state of a group of bus lines when they carry signals. 2.2.2 address-only transaction: A bus transaction
18、that does not include a data phase. The only information transferred is contained within the connection phase and, in some cases, the disconnection phase. 2.2.3 arbitration: The process of selecting the next bus master. 2.2.4 arbitrated message: A number broadcast on the arbitrated message bus lines
19、 to all modules on the bus. 2.2.5 assert: a) The action of applying a logic one signal to a bus line. b) The state of a bus line when the signal it carries represents a logic one. 2.2.6 * (asterisk): When appended to a signals name, the suffix “*” indicates that the logic one state of the signal is
20、such that it will override the logic zero state applied by any other module on that line. 2.2.7 beat: An event that begins with the transition on a synchronization line by the master, followed by the release of an acknowledge line by one or more slaves. Command and data information may be transferre
21、d from the master to one or more slaves in the first half of the beat. During the second half of the beat the slaves may transfer capability, status, and data information back to the master. 2.2.8 block copy: A block copy operation is characterized by a long series of read or write transactions to s
22、equential memory locations. 2.2.9 bus bridge: A bus bridge is an interconnect between two or more buses that provides signal and proto- col translation from one bus to another. The buses may adhere to different bus standards for mechanical, electrical, and logical operation (such as a bus bridge fro
23、m Futurebus+ to VMEbus or to MULTIBUS II). 2.2.10 bus line: The medium for the transmission of signals. Since Futurebus+ requires drivers with wire- OR capability, a bus line may be driven by several modules simultaneously. Therefore, the signal carried by the bus line is the combination of signals
24、applied to that line from each module. 2.2.11 bus tenure: The duration of a masters control of the bus; i.e., the time during which a module has the right to initiate and execute bus transactions. 4 Copyright International Organization for Standardization Provided by IHS under license with ISONot fo
25、r ResaleNo reproduction or networking permitted without license from IHS-,-,-ISO/IEC 10857 : 1994 (E) FUTUREBUS+ - LOGICAL PROTOCOL SPECIFICATION ANSI/IEEE Std 896.1, 1994 Edition 2.2.12 bus transaction: An event initiated with a connection phase and terminated with a disconnection phase. Data may o
26、r may not be transferred during a bus transaction. See: transaction. 2.2.13 busy: If a slave is unable to accept a bus transaction from a master, it may issue a busy status to the master of the transaction. The master must relinquish the bus and may reacquire the bus and retry the trans- action afte
27、r a suitable time interval. 2.2.14 byte: A set of eight adjacent binary digits. 2.2.15 byte lane: A data path formed by eight data lines and one parity line and used to carry a single byte between system modules. 2.2.16 cache coherence: A system of caches is said to be coherent with respect to a cac
28、he line if each cache and main memory in the coherence domain observes all modifications of that same cache line. A modifica- tion is said to be observed by a cache when any subsequent read would return the newly written value. 2.2.17 cache memory: A buffer memory inserted between one or more proces
29、sors and the bus, used to hold currently active copies of blocks from main memory. Cache memories exploit spatial locality by what is brought into a cache. Temporal locality is exploited by the strategy employed for determining what is removed from the cache. 2.2.18 coherence domain: A region in a m
30、ultiple-cache system, inside of which, cache consistency mea- sures are enforced. In a system that contains bus bridges, a coherence domain may or may not be extensible beyond the local bus through a bus bridge to remote buses. 2.2.19 coherence line: A data block for which cache consistency attribut
31、es are maintained. 2.2.20 compelled data transfer protocol: A technology-independent transfer mechanism in which the slave is compelled to provide a response before the master proceeds to the next transfer. 2.2.21 competitor: A module actively participating in the current control acquisition cycle o
32、f the arbitration process. 2.2.22 connected transaction: A transaction in which both the request and response are performed within the same bus transaction. 2.2.23 connection phase: A beat that begins with the assertion of the address synchronization line followed by the release of an address acknow
33、ledge line. It is used to broadcast the address and command information. Modules determine whether they wish to take part in the transaction based on this information. 2.2.24 control acquisition: The total of all bus activity associated with acquiring exclusive control of the bus. 2.2.25 copyback ca
34、che: A cache memory scheme with the attribute that data written from the processor is normally written to the cache rather than the main memory. Modified data in the cache is written to the main memory to avoid loss of the data when a cache line flush or replacement occurs. 2.2.26 CSR: Control and s
35、tatus register. 2.2.27 CSRA: Control and status register architecture. (See IEEE Std 1212-1991 B7.) 2.2.28 data phase: A period within a transaction used to transfer data. 5 Copyright International Organization for Standardization Provided by IHS under license with ISONot for ResaleNo reproduction o
36、r networking permitted without license from IHS-,-,-ISO/IEC 10857 : 1994 (E) ANSI/IEEE Std 896.1, 1994 Edition MICROPROCESSOR SYSTEMS- 2.2.29 deadlock: A state that occurs when modules are awaiting actions that can only be performed by those waiting, and those waiting cannot perform the actions. 2.2
37、.30 disconnection phase: A period within a transaction used to return the bus signals to their quiescent state. In addition, this phase might be used to transfer additional information required to perform or abort the requested operation. 2.2.31 doublet: A set of two adjacent bytes. 2.2.32 entrant:
38、A live inserted module in the process of aligning itself with the arbitration protocol. 2.2.33 forward progress: A state in which a module is not blocked from performing the tasks necessary to achieve its goal. Forward progress is guaranteed only in the absence of deadlock or starvation. 2.2.34 geog
39、raphical address: A unique identifier assigned to each physical module slot on the bus and assumed by any module connected to that slot. 2.2.35 global identification: A unique identifier assigned to each physical module slot in a system. This identifier would typically include both a bus identifier
40、and a slot identifier. IEEE Std 1212- 199 1 B7 speci- fies the format for such a global identifier. 2.2.36 intervening slave: The participating slave that, although not the repository of last resort of the requested data, finds it necessary to prevent the repository of last resort from providing the
41、 requested data. Having done so, the intervening slave provides the data instead. 2.2.37 livelock: A metastable situation in which some modules acquire and release resources in such a way that none of them makes forward progress. 2.2.38 locking: A facility whereby a module is requested to guarantee
42、exclusive access to addressed data, blocking other modules from accessing that data. This allows indivisible operations to be performed on addressed resources. 2.2.39 master: A module that has acquired control of the bus through the control acquisition procedure. 2.2.40 master elect: A module that h
43、as won the most recent arbitration competition. 2.2.41 module: A collection of circuitry designed to perform specific functions that include an interface to Futurebus+. 2.2.42 monarch processor: The processor selected to manage the configuration and initialization of all modules on one logical bus.
44、Also: monarch. An emperor processor is the monarch processor selected to direct the configuration and initialization of an entire system with multiple interconnected logical buses. 2.2.43 octlet: A set of eight adjacent bytes. 2.2.44 packet data transfer protocol: A very fast but technology-dependen
45、t noncompelled transfer mecha- nism that uses a compelled protocol over the entire packet to provide flow control. 2.2.45 parallel contention arbitration: A process whereby modules assert their unique arbitration number on a parallel bus and release signals according to an algorithm such that after
46、a period of time the winners number appears on the bus. 2.2.46 participating slave: A slave involved in a transaction as a selected slave, an intervening slave, a broadcast slave, or a slave involved in multiple packet mode. Copyright International Organization for Standardization Provided by IHS un
47、der license with ISONot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ISO/IEC 10857 : 1994 (E) FUTUREBUS+ - LOGICAL PROTOCOL SPECIFICATION ANSI/IEEE Std 896.1, 1994 Edition 2.2.47 preemption: The release of the bus by the current bus master due to the request of anot
48、her module. NOT in others, only a module with a higher priority request may cause preemption. 2.2.48 quadlet: A set of four adjacent bytes. 2.2.49 release: a) The action of applying a logic zero signal to a bus line. b) The state of a bus line when the signal it carries represents a logic zero. 2.2.
49、50 repository of last resort: In a hierarchical memory (or cache-based) environment, a storage location that “owns” the only, or last remaining, copy of sharable data. NOTE-It may be a unique source, an ultimate destination, or simply a “safe” repository of data that may not be invali- dated, unless action is taken to preserve a copy of that data at some higher level in the memory (or cache) hierarchy. In a cache-only Futurebus+ system (e.g.,
