1、Digital Design and SynthesisCOEN 6501,Lecture_1 In this lecture we will review: The Digital Design process Introduce and review Adders The Carry Ripple Through Adder The Carry Look Ahead Adder,System Design Description,Systems are described in terms of three domains:Behavioural domain Structural dom
2、ain Physical domain,Structural,Behavioural,Physical,Logic Synthesis,Physical Synthesis,Structural,Behavioural,Physical,System,Algorithmic,Micro architecture,Logic,Circuit,Rectangles,Cells,Macro-cells,Modules,Chips, boards,Processor,Hardware modules,ALU, registers,Gates, F/Fs,Transistors,Systems,Algo
3、rithms,Register transfer,Logic Equations,Transfer function,Logic synthesis,Physical synthesis,Expected power savings in logic synthesis at various levels of design flow,Optimization Levels,Design Process:It starts with behavioural description, decomposingthe high level of constructs into more precis
4、e functionalunits, then mapping these units into physical elements.,System Specification,Architectural Design (behavioural),Analysis,Design Implementation (structural),Analysis,Design Implementation (Physical),Analysis,Design Strategies,Hierarchy A repeated process of dividing large modules into sma
5、ller sub-modules until the complexity of sub-modules are at an appropriately comprehensible level of detail. Parallel hierarchy is implemented in all domains.,Regularity Divide the hierarchy in to similar building blocks whenever possible. Some programmability could be added to achieve regularity. M
6、odularity Well defined behavioural, structural and physical interface. Helps: divide tasks into well defined modules, design integration, aids in team design. Locality Internals of the modules are unimportant to any exterior interface.,A Structured Design,System Design Methodology,Market Analysis,Sy
7、stem Specifications,System Architecture,System Partitioning,Market windows System features & requirements Standards,Functional Electrical Mechanical Environmental,Strategies Modelling Verification,Dictated by complexity, I/O pins, off-the-shelf components, special requirements Partitioning guideline
8、s Partitioning approaches: vertical, horizontal, functional, performance,Testability,Technology Selection,Detailed Design,Implementation,Strategies, chip testing, board testing Testability features Penalties,Dictated by: speed, power dissipation, driving capability,cost, lead time,Logic design/synth
9、esis Optimization Verification,Off-the-shelf ICs Application Specific ICs,Assembly,Testing,Documentation,Production,Decide on packaging technical components Design/manufacture Components Electrical/mechanical assembly Mechanical assembly & components sales,Functional DC test AC test Burn-in,Technica
10、l documents H/W & S/W & mechanical User manual Test document,13,Verify at every step,Layout,Device,Circuit,Logic,Structural,Functional,IC Design Methodology,Requirement specification most important function which impacts the ultimate success of an IC relates to how firm and clear the device specific
11、ations are. Device specification may be updated throughout the design cycle. Main items in the specifications are: functional intent: brief description of the device, the technology and the task it performs. Packaging specification device port number package type, dimension, material,Functional desc
12、ription high-level block diagram: all major blocks including intra block connections and connections to pin-outs indicating direction and signal flow.Intra block signal function: description of how blocks interact with each other supported with timing diagram where necessary.Internal block descripti
13、on of internal operation of each block. Where necessary, the following to be included: timing diagram, state diagram, truth table.,Functional Description,I/O specifications pin-out diagram I/O functional description loading ESD requirements latch-up protection D.C. specifications absolute maximum ra
14、tings for: supply voltage, pin voltages main parameters: VIL and VIH for each input, VOL and VOH for each output, input loading, output drive, leakage current for tri-state operation, quiescent current, power-down current (if applicable),Specifications,AC specifications inputs: set-up and hold times
15、, rise and fall times outputs: propagation delays, rise and fall times, relative timing critical thinkingEnvironmental requirements operating temperature, storage temperature, humidity condition (if applicable)Testing,Specification, continued,Device Specification,Functional intent: briefly describe
16、the device, the technology, and the circuits it will replace as well as the task it will perform. Design concept pin-out diagram: describe the device using a block diagram of the external view of the chip - basically, a box with all the I/O pins labelled and numbered I/O description: use a chart to
17、define the I/O signals shown in the pin-out diagram,Example:,internal block diagram: draw blocks for major functions, show all connections including: connection to all pin-outs, connections between blocks, and direction of signal flow Inter-block signal function: describe how the blocks interact wit
18、h each other and support this with timing diagrams where necessary internal block description: describe the internal operation of each block. When necessary, include: timing diagrams, state diagrams, and truth table,Logic description: circuit schematic or logic diagram using standard cell library co
19、mponents,Package description: device port number, package type, dimensions, materials,Functional Specification,Operating characteristics Absolute maximum stress ratings. Example:,Operating power and environmental requirement:power supply voltage operating supply current (specify conditions, e.g., po
20、wer up, power down, frequency, output conditions) storage temperature operating temperature humidity conditions (if applicable),Requirements,Input characteristics. Example chart: (V reference is VSS = 0, temperature range is 0oC to 70oC),Output Interface Characteristics Example chart: (VSS = 0, T ra
21、nge 0oC to 70oC,AC description Timing diagram: include well-labelled signal drawings of all significant input and output relationships, rise and fall times, data set-up and hold times. Indicate the voltage range over which timing must be guaranteed,Definitions:,Cout,input,output,VIH,VIL,Set-up,hold,
22、hold,VIH,VIL,Example: timing diagram and chart,RXCK,RXFRM,RXIN,t19,t20,t22,t21,t17,t18,t16,Specs (continued),Critical Path,Signal paths with tight timings (if applicable) potential race conditions (if applicable) any set of paths with the same source and destination such as a clock signal and its co
23、mplement (if applicable),Test Description,Test strategy: written description of functions to be tested. This section is a guide for determining and explaining simulation patterns simulation input/output patterns: timing diagrams which include stimulus to be applied to input pins and the expected res
24、ponse on the output pins,Example : Multiplicand = 100010012 = 8916 Multiplier = 101010112 = AB16 Expected Result = 1011011100000112 =5B8316,System Level Design,Top down approach Using behavioural constructs, top level architecture is defined Design validation is technology independent Use HDL to mod
25、el the design (e.g., VHDL and Verilog) RTL is efficient for describing data flow,Timing verification is difficult unless structure logic is definedVHDL representation can be changed into structural logic through - manual design, design synthesis: automated process which involves the conversion of VH
26、DL/RTL into a set of registers and combinational circuits,System Level design (Continued),Synthesis report,Area report after Synthesis,Power report after Synthesis,Timing Report After Synthesis,37,AIMs,What the CUSTOMER wants High Quality Low CostSmall Size/WeightWhat the EMPLYER wants Design the: B
27、est Cheapest In shortest time Follow the Spec or better.What you CHIP DESIGNER should do: Design a chip with: High speed Small area Low power Testable and reliable Delivered in a short time,Logic Design,Evaluation of library constructs (basic & macro) function, timing, area Logic minimization NAND/N
28、OR transformation Buffering Fan-out reduction Fan-in reduction,Critical timing Priority routing I/O compatibility Logic optimization Cost function: area, speed, power, or a combination,Logic Level design (Continued),Logic Simulation,Simulation is the process of exercising a theoretical model of the
29、design as a function of time for some applied input sequenceLogic simulation is to aid in verification of a digital system,Componentsmodels: functional, timing connectivity: a description of how the basic components are connected together stimulus: 1s and 0s that are applied at specific times to the
30、 primary inputs of the design simulation controlStates: basic (0, 1, X), strength could be combined with basic; strong (S), resistive (R), high impedance (Z), indeterminate (I),Logic Simulation (Continued),Simulation model- logical,* * Library: ACME * Technology: 2u CMOS * Part: fdrc * * Description
31、: D flip-flop with rising edge, async. Clear *model fdrc: table input d, rn; edge_sense input cp; output q, qn;,State_tablern, cp, d, q : q, qn; * -0, (?), ?, ? : 0, 1,1, (01), ?, ? : (d), !(d);1, (?0), ?, ? : N, !(q);1, (1?), ?, ? : N, !(q);end (fdrc: table);,Timing Verification,Process of making a
32、ccurate delay prediction and to detect timing violation in the design. These violations include set-up time, hold time, races and spikes.Delay through the circuit is a function of: intrinsic delay number of loads connected to each net temperature voltage process variation, layout Typically, best and
33、 worst case scenarios should be considered.,Simulator uses a set of equations to calculate exact delays,Fan-out td = t(int) + K*L t(int) = intrinsic delay K = drive factor L = sum of equivalent loads,temperature td = td/FT FT = (T2/T1) -Mvoltage td = td/VDDr(1 + 0.0f)process td = td(1 + 0.01Fp), Fp
34、= = processing variation factorlayout information is normally supplied in two forms: pre-layout estimation post-layout: back annotation,Timing Verification (Continued),hazards spikes: inertial and transport delaysset-up time/hold time/minimum pulse width,tPLH = 2 tPHL = 1,inertial,transport,Timing,C
35、ritical path analysis detection of timing violation for data path structure the process is simply adding up path delays and compute the result with the period of the clock at the destination (F/F) path analysis is not simulation and does not utilize information about the functionality of the device
36、look for two parameters hold slack = clock period - hold path time set up slack = clock period - set up path time slack = 0 paths are chosen to provide the least amount of available set up or hold times,Timing,Structural layout synthesis,Floor planning it is the exercise of arranging blocks of layou
37、t within a chip to minimize area or to maximize speed floor plan editors provide graphical feedback about the size and placement of modules (without showing details), also the connectivity information between the modules in the form rats-not floor planning could be done manually, or automatically wi
38、th manual intervention factors influencing floor planning (core & I/Os),A,B,C,D,Placement and routing,Placement: is the task of placing modules adjacent to each other to minimize area or cycle time two algorithms: min-cut, simulated annealing routing: a router takes a module placement and a list of
39、connections, connects the modules with wires types of routers: channel, switch box, maze,inv,inv,reg,nd2,nd2,nd2,nd2,nd2,nd2,nd2,nd2,inv,inv,inv,inv,inv,reg,nd3,nd3,nd3,Channel route,Channel route,Other layout tools synthesis compaction Layout verification design rule checking layout extraction layo
40、ut vs. schematic Back annotation of post layout simulation,Layout,to verify the correct operation of the device by exercising it by a set of test patterns, and then to check the output patterns to see whether they are identical to the ones predicted by the simulatortester also verifies DC and AC par
41、ameters on the pins of the device,comparator,DUT,X 0 1 1 0 1 0 1 Z 1 1 1: : : :,0 1 1 0 0 1 : :,from simulator,o/p,i/p,Testing,Tester operates in a periodic fashion input signals charge states at the beginning of the test period output signals are strobed at the end of the period to determine whethe
42、r the measured values matches the simulated values,T0,T0,T0,Test cycle,i/p,o/p,strobe,Timing Analysis,Types of Testing,Functional (mostly at lower speeds) static dynamic (refresh if required) DC test continuity leakage, power consumption high/low voltage levels, drive capability AC test rise/fall ti
43、mes, propagation delays set-up and hold times, access times,Functional unit,Functional unit,Functional unit,Processor,register,register,register,LOGIC,CIRCUIT,LAYOUT,FABRICATION,COEN 7501 Formal Verification,ENCS 6521 Design for Testability,ELEC 6231,COEN 6531 ASIC Synthesis,ENCS 6511,ELEC 6241,ELEC
44、 6501,COEN 7741 Advance Comp. Arch,Binary Arithmetic,Example: design an addition overflow circuit, in accordance with the following specification:,When the operation is addition and both addend and augend are +ve, overflow is indicated by a carry from the most significant digit (MSD) when the operat
45、ion is addition and both addend and augend are -ve, overflow is indicated by the absence of carry from the MSD when the operation is subtraction and the minuend is +ve and the subtrahend -ve, overflow is indicated by a carry from the MSD when the operation is subtraction and the minuend is -ve and subtrahend is +ve, overflow is indicated by absence of a carry from the MSD,THE END,
