1、Targeting Tiled Architectures in Design Exploration,Lilian Bossuet1, Wayne Burleson2, Guy Gogniat1,Vikas Anand2, Andrew Laffely2, Jean-Luc Philippe1,Outline,Introduction: Design Space ExplorationDesign Space of Reconfigurable ArchitectureA Target Architecture: aSoCProposition of Design Space Explora
2、tion FlowResultsConclusion and Future Work,Design Space Exploration: Motivations,Design solutions for new telecommunication and multimedia applications targeting embedded systemsOptimization and reduction of SoC power consumptionIncrease computing performance Increase parallelism Increase speedBe fl
3、exible Take into account run-time reconfiguration Targeting multi-granularity (heterogeneous) architectures,Design Space Exploration: Flow,Progressive design space reduction: iterative exploration refinement of architecture model increase of performance estimation accuracyOne level of abstraction fo
4、r one level of estimation accuracy,Outline,Introduction: Design Exploration Flow PrincipeDesign Space of Reconfigurable ArchitectureA Target Architecture: aSoCProposition of Design Space Exploration FlowResultsConclusion and Future Works,Reconfigurable Architectures,Bridging the flexibility gap betw
5、een ASICs and microprocessor Hartenstein DATE 2001Energy efficient and solution to low power programmable DSP Rabaey ICASSP 1997, FPL 2000Run Time Reconfigurable Compton & Hauck 1999= A key ingredient for future silicon platforms Schaumont & all. DAC 2001,Design Space of Reconfigurable Architecture,
6、RECONFIGURABLE ARCHITECTURES (R-SOC),FINE GRAIN (FPGA),MULTI GRANULARITY (Heterogeneous),COARSE GRAIN (Systolic),Processor + Coprocessor,Tile-Based Architecture,Coarse Grain Coprocessor,Fine Grain Coprocessor,Island Topology,Hierarchical Topology,Linear Topology,Hierarchical Topology,Mesh Topology,C
7、hameleonREMARCMorphosys,PleiadesGarpFIPSOCTriscend E5Triscend A7Xilinx Virtex-II ProAltera ExcaliburAtmel FPSIC,Xilinx VirtexXilinx SpartranAtmel AT40KLattice ispXPGA,Altera StratixAltera ApexAltera Cyclone,Systolic RingRaPiDPipeRench,DARTFPFA,RAWCHESSMATRIXKressArraySystolix Pulsedsp,aSoCE-FPFA,Out
8、line,Introduction: Design Exploration Flow PrincipeDesign Space of Reconfigurable ArchitectureA Target Architecture: aSoCProposition of Design Space Exploration FlowResultsConclusion and Future Works,A Target Architecture: aSoC,Adaptive System-on-a-Chip (aSoC)Tiled architecture containing many heter
9、ogeneous processing cores (RISC, DSP, FPGA, Motion Estimation, Viterbi Decoder)Mesh communication network controlled with statically determined communication scheduleA scalable architecture.,tile,FPGA,uProc,MUL,MUL,Heterogeneous Cores,aSoC Architecture,aSoC Communications Interface,Core,Coreports,De
10、coder,Local,Frequency,& Voltage,North to South & East,Instruction Memory,PC,Controller,North,South,East,West,Local,Config,.,North,South,East,West,Inputs,Outputs,Interface Crossbar inter-tile transfer tile to core transfer Interconnect/Instruction Memory contains instructions to configure the interfa
11、ce crossbar (cycle-by-cycle) Interface Controller selects the instruction Coreports data interface and storage for transfers with the tile IP core Dynamic Voltage and Frequency Selection Dynamic Power Management,Interface Crossbar,aSoC Exploration .,Type of tilesNumber of each type of tilePlacement
12、of the tilesIntern architecture of reconfigurable tiles (FPGA core)Communication scheduling,Outline,Introduction: Design Exploration Flow PrincipeDesign Space of Reconfigurable ArchitectureA Target Architecture: aSoCProposition of Design Space Exploration FlowResultsConclusion and Future Work,Design
13、 Space Exploration: Goals,Goal: Rapid exploration of various architectural solutions to be implemented on heterogeneous reconfigurable architectures (aSoC) in order to select the most efficient architecture for one or several applications Take place before architectural synthesis (algorithmic specif
14、ication with high level abstraction language) Estimations are based on a functional architecture model (generic, technology-independent) Iterative exploration flow to progressively refine the architecture definition, from a coarse model to a dedicated model,Design Exploration Flow Targeting Tiled Ar
15、chitecture,Application Analysis,Use of algorithmic metrics and dedicated scheduling algorithms to highlight the target architectures Algorithmic metrics: Characterize the application orientation Processing Memory Control Characterize the application potential parallelism Processing Memory,Tile Explo
16、ration: with 3 steps,Projection: Link between necessary resources (application) and available resources (tile) Use of an allocation algorithm based on communication costs reductionComposition: Take into account of the function scheduling to estimate additional resources (register, mux, ) Estimation:
17、 performance interval computation (lower and upper bounds) speed/resource utilization/power characterization,aSoC Builder,Environment AppMapperPartition and assignment based on Run Time EstimationCompilation Communication Scheduling Core compilationGenerate tiles configuration Communications instruc
18、tions Bitstreams (for reconfigurable tile) RISC instructions,aSoC Analysis,Use the results of previous steps Functions scheduling Tile allocation Communication schedulingComplete estimation of the proposed solution Global execution time Global power consumption Total area,Outline,Introduction: Desig
19、n Exploration Flow PrincipeDesign Space of Reconfigurable ArchitectureA Target Architecture: aSoCProposition of Design Space Exploration FlowResultsConclusion and Future Work,Results,aSoC architecture (UMASS) Prototype of aSoC interconnect Technology 0.18 m Clock speed of 400 MHzAppMapper (UMASS) Se
20、veral mapped applications Matrix operations Median Filter Viterbi decoder DCT,Tile exploration (UBS) Application analysis Intelligent Camera (motion detection) Matching Pursuit Projection step Lee DCT Matrix operations,Outline,Introduction: Design Exploration Flow PrincipeDesign Space of Reconfigura
21、ble ArchitectureA Target Architecture: aSoCProposition of Design Space Exploration FlowResultsConclusion and Future Work,Conclusion and future work,Conclusion Original design exploration flow working at a high level of abstraction Fast and flexible (use of functional view of the architectures) Targe
22、ting an efficient reconfigurable architecture: aSoC Statically-scheduled, point-to-point communicationsFuture Work Development of larger set of design exploration benchmarks Exploration of other configurable systems,Thank you .,Previous Work,Xplorer - University of Kaiserslautern, Germany Hartenstei
23、n PATMOS 2000 Targets a mesh coarse grain architecture: The KressArray a fast reconfigurable ALUs Gives design guidance concerning: the size of the array, the available operators, the communication architecture and the connection structure. Controlled by performance and power estimations. Starts wit
24、h high level specification of application (ALE-X language).RAW - Massachusetts Institute of Technology, USA Moritz FCCM 1998 Targets a reminiscent coarse grained FPGA: The MIT Raw Microprocessor Answers to the balance problem: to determine the best division of VLSI resources among computing, memory
25、and communication. Answers to the grain problem: to determine the optimum size of each architecture tiles Use several models: architecture model, costs model and performance model,HCDFG: Hierarchical Control Data Flow Graph,Applications Metrics,Y. Le Moullec, N. Ben Amor, J-Ph. Diguet, M. Abid and J-L. Philippe. Multi-Granularity Metrics for the Era of Strongly Personalized SOCs. In DATE 2002, Munich, Germany, March 2002,
