1、IINCH-POUND 1 MIL-C-48481C(AR) ?see 6.4) O Mav 1995 MILITARY SPECIFICATION CIRCUIT CARD ASSEMBLY - FTS INPUT SIMULATER AND DL TEST This specification is approved for use by the US Army Armament, Research, Development and Engineering Center (ARDEC) and is available for use by all Departments and Agen
2、cies of the Department of Defense. 1. SCOPE 1.1 Scope. This specification establishes the requirements and quality assurance provisions for the Circuit Card Assembly FTS Input Simulater and DL Test, 11732520 (See 6.1). 2. APPLICABLE DOCUMENTS 2.1 Government documents. 2.1.1 Specifications, standards
3、, and handbooks. The following specifications, standards, and handbooks form a part of this document to extent specified herein. Unless otherwise specified, this issue of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DODISS) and sup
4、plement thereto, cited in the solicitation (see 6.2). SPECIFICATIONS MILITARY MIL-F-13926 - Fire Control Materiel, General Specifications Governing the Manufacture and Inspection of MIL-1-45607 - Inspection Equipment; Acquisition, Maintenance, and Disposition of Beneficial comments (recommendations,
5、 additions, deletions) and any pertinent data which may be of use to improving this document should be addressed to: Commander, U.C. Army ARDEC, ATTN: AMCTA-AR-EDE-S, Picatinny Arsenal, New Jersey 07806-5000 by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the e
6、nd of this document or by letter. AMSC NIA FsC 1240 DISTBLBVTI ON STATEMENT A . Approved for public release; distribution is unlimited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-P STANDARDS MILITARY MIL-STD-100 MIL-STD-454 MIL-STD-810 MIL-STD-2
7、000 MIL-STD-2073-1 - Engineering Drawing Practices - Standard General Requirements for - Environmental Test Methods - Standard Requirements for Soldered - Procedures for Development and Electronic Equipment Electrical and Electronic Assemblies Application of Packaging Requirements (Unless otherwise
8、indica-ed, copies of federal and military specifications, standards, and handbooks are available from: DODSSP - Customer Service, Standardization Documents Order Desk, 700 Robbins Avenue, Bldg 4D, Philadelphia, PA 19111-5094.) 2.1.2 Other Government documents, drawinqs, and publications. The followi
9、ng other Government documents, drawings, and publications form a part of this document to the extent specified herein. Unless otherwise specified, the issues are those cited in the solicitation. U.S. Army Armament Research Development and Engineering Center (ARDEC) DRAWINGS 11732520 - Circuit Card A
10、ssembly - FTS Input Simulater and DL Test (Copies of Government drawings required by contractors in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) the test of this document and the references cited herein (
11、except for related associated detail specifications, specification sheets, or MS standards), the test of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained, (See control provisions for additional
12、 precedence criteria). 2.2 Order of precedence. In the event of a conflict between 3 . REQUIREMENTS 3.1 Fabrication. The FTS Input Simulater and DL Test circuit card assembly, herein referred to as the assembly, shall be manufacture; in accordance with Drawing 11732520 and drawings pertaining theret
13、o and, when assembled, shall meet the requirements of this specification (see 4.5.1). 2 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-3.1.1 Function, The assembly shall provide the following Eunctions: a. Simulate input signals sent to the computer
14、 in the b. Provide circuitry to illuminate incorrect setup and system configuration. Test in Progress indicators in the Field Test Set panel. 3.1.2 General specifications. (see 4.6.3) 3.1.2.1 Manufacture and inspection. The following provisions of MIL-F-13926 apply: a. Dimensions and tolerances b. E
15、ffect of protective coating on dimensions (Inorganic c. Part identification and marking d. Workmanship (Including applicable portions of type coating) MIL-STD-2000 and MIL-STD-454, Requirement 9) 3.1.2.2 Standards of manufacture. 3.1.2.2.1 Assembly and solderinq. The requirements of MIL-STD-2000 sha
16、ll apply, as a minimum. 3.1.2.2-2 Interchangeability. The assembly shall be manufactured in accordance with interchangeability requirements as specified in MIL-STD-109. 3.1.3 Ambient conditions. Standard ambient conditions shall be as follows: a. Temperature 730 + 180F b. Relative Humidity 50 percen
17、t - + 30 percent c. Atmospheric pressure 28.5 + 2.0 -3.0 in. Hg. 3.2 First Article. When specified in the contract or purchase order (see 6.21, the contractor shall furnish sample - units for first article inspection and approval (see 4.4). 3.3 Performance. Unless otherwise specified, the assembly s
18、hall meet the performance requirements specified herein under standard ambient conditions of 3.1.3. - 3.3.1 Lamp and phase test logic. With the power sources (items 2.1 and 2.4 of Table I) the loads (item 1.1 and 1.2 of Table I) and the interconnections (item 4.1 of Table I) applied to the assembly:
19、 and with each of Table II items input conditions established in any item order, the corresponding ordered output conditions shall be as specified herein (see 4.6.1.1). 3 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- MIL-C-448LC m 9999906 2004853
20、495 MIL-C-48481C(AR) TABLE I. Loads, power, siqnals, and interconnections. Item Conditions Characteristics Connections 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 2.0 2.1 2.2 2.3 2.4 Loads Lamp Lamp Resistor Resistor Resistor Res i st or Re sis tor Re sis tor Resi
21、stor Res is tor Resistor Res is tor Res i stor Resistor Res is tor Re sis tor Res is tor Power sources 24V dc 15V dc 1OV dc 5.25V dc 24V lamp in series with 24V dc (Item 2.1) 24V lamp in series with 24V dc (Item 2.1) 100 kilohms +0.05%, 1/10 watt (w7 1OOK ohm + 1%, 1/1Ow 100K ohm 1%, 1/1Ow 100K ohm
22、1%, 1/1Ow 100K ohm T 1%, 1/1Ow 1OOK ohm 1%, 1/1Ow 100K ohm 1%, 1/1Ow 200R ohm 7 1%, 1/1Ow 50K ohm T 1%, 1/1Ow 73.4R ohm+ 1%, 1/1Ow 1000.1R ohm + 1%, 1/8w 20R ohm + 1%; 1/1Ow 247K ohm-+ 1%, 1/1Ow 70K ohm +-i%, 1/1Ow 30.9K oh% - + 1%, 1/1Ow Tolerance: +2V dc Ripple 0.200v peak- to peak (p-p) max Curre
23、nt: 500 ma min Tolerance: +O.O30V dc Ripple 2OmV 5-p max Current: 500ma min Tolerance: +O. 010V dc Ripple 20mV E-p max Current: 500 ma min Tolerance: +O.l5OV dc Iiippe 20mv jj-p max Current: 500 ma min Connected between the following pins: A16(-) and 24V dc (see Item 2.1) A17(-) and 24V dc (see Item
24、 2.1) A8 and A3 B5 and A3 B7 and A3 A5 and A3 B20 and A3 A20 and A3 A24 and A3 A22 and A3 A19 and A3 B26 and A3 B3 and A3 B25 and A3 B19 and A3 B2 and A3 B23 and A3 Applied between pin(s1: A15(-) and load lamps, Items 1.1 and 1.2(+) Al(+) and A3(-) A7(+) and A3(-) A30(+) and A13(-) Provided by IHSNo
25、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-C-48481C(AR) TABLE I. Loads, power, signals and interconnections. - Continued Item Conditions Characteristics Connections 2.5 -lOV dc 2.6 -15V dc 3.0 Signal sources 3.1 15V dc 3.2 5V dc 3.3 -15V dc 3.4 5.000V rms 40
26、0 Hz 3.5 5.000V rms 3.6 Selectable: 1.500 to 5,OOOV rms, 400 Hz 3.7 Selectable: O to 5.000V rms 400 Hz 3.8 2.000V rms, 400 Hz +15V, 400 Hz 3.9 - (MR1) Tolerance: +O.OlOV dc Ripple 20mv 5-p max Current: 500 ma min Tolerance: +O.O30V dc Ripple 20mV E-p max Current: 500 ma min Tolerance: +0.150V dc Rip
27、ple 20mV 6-p max Current: 500 ma Tolerance: +O.Sv dc Ripple 0.020v p-p max Current: 500 ma Tolerance: +0.150V dc Ripple 20mV p-p max Current: 500 ma Tolerances: +O.O05V rms; + 1 Hz Phase? 1 Tolerances: +O.O05V rms; + 1 Hz Phase? 2 (1800 out of phase with phase 1 in item 3.4) Tolerances: +0.005V rms;
28、 5 1 Hz ?hase: 1 - - - Tolerance: as specified, + 1 Hz Phase: 2 Tolerances: - +O.O03V rms: +Hz Phase: 1 Square wave Tolerance: - +O.SOV; +1 Hz Phase: 1 - - - Alo(-) and A3(+) A4(-) and A3(+) Applied as specified with return to A3(-) Applied as specified with return to A13, Applied as specified with
29、return to A3(+) B13(-) Applied as specified between A2 and A3 Applied as specified between A2 and A3 Applied as specified between A26 and A3 Applied as specified between A27 and A3 Applied as specified between B10 and A3 Applied to pin P1-B6 with return to pin P1-A3 5 Provided by IHSNot for ResaleNo
30、 reproduction or networking permitted without license from IHS-,-,-MIL-C-48481C input Conditions at Pins i/ - Item B17 B18 A18 B16 B15 B14 A14 . 0b 2004855 268 Output Conditions Lamp 2/ Pins 3/ Al6 A17 A12 B12 A23 MIL-C-48481C(AR) TABLE I. Loads, power, signals and interconnections. - Continued Item
31、 Conditions Characteristics Connections +15V, 400 Hz Square wave Applied to pin P1- (MR2 ) Tolerance: - +0,50V; B30 with return to 3.10 - - + 1 Hz; P1-A3 Phase: 2 (1800 cut-of-phase with phase 1 in item 3.9) 4.0 interconnections 4.1 A3, A13, B13, and Al 5 TABLE II. Lamp and phase test logic. 1 1 1 1
32、 1 O 1 O 2 O 1 1 1 O 1 O 3 1 O 1 1 O 1 N/Ag 4 1 1 O 1 O 1 1 5 N/A N/A O O O 1 N/A 6 N/A N/A N/A O 1 O N/A O 1 1 1 O O 1 o N/A 1 O O O 1 N/A 1 o N/A - i/ 1 = 5.0 + 0.5V dc (Item 3.2 of Table I); O = 0.0 - + 0.5V dc, interconnected with pins A13, B13 - 2/ X = illuminated; - - not illuminated - 3/ 1 =
33、5.0 +0.5/-2.6V dc; O = 0.0 5 0.5V dc - 4/ N/A = not applicable condition 3.3.2 01, comparator logic. With the power forms (items 2.2 through 2.6 of Table I), and with input signals (items 3.7, 3.9 and 6 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,
34、-. 3.10 of Table I) and the interconnections (item 4.1 of Table I) applied to the assembly, and with the input signal voltage (item 3.7 of Table I) adjusted to nominal voltage and with other input conditions applied as specified in Table III in any item number order, the following shall occur when c
35、onditions are applied in the sequence below (see 4.6.1.2). a. With an increase in the signal input voltage (item 3.7 of Table I) from nominal voltage, the output voltage at pin B11 shall switch from logic level zero, 0.0 + 0.5V dc, to logic level one, 5.0+ 0.50/-2.60V dc. outward bound upper limit r
36、ange as specified in Table III. The input voltage shall fall within the b. With a decrease in the signal input voltage (item 3.7 of Table I) from the outward bound upper limit, the output voltage at pin B11 shall switch from logic level one, 5.0 + 0.50/-2.60V dc, to logic level zero, 0.0 + 0.5OV dc.
37、 The input voltage shall fall within the inward bound uFper limit range as specified in Table III. c. With a decrease in the signal input voltage (item 3.7 of Table I) from the inward bound upper limit, the output voltage at pin B11 shall switch from logic level zero, 0.0 + 0.5OV dc, to logic level
38、one, 5.0 + 0.50/-2.6OV dc. The input voltage shall fall within the outward bound lower limit range as specified in Table III. d. With an increase in the signal input voltage (item 3.7 of Table I) from the outward bound lower limit, the output voltage at pin B11 shall switch from logic level one, 5.0
39、 + 0.50/-2.60V dc, to logic level zero, 0.0 + 0.5V dc. The input voltage shall fall within the inward bound lower limit range as specified in Table III. 7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-i a O .rl c, 8 c, -4 i4 u -4 MIL-C-4848LC -=rw
40、o ON O0 ?*? e* di o4 O0 PU-“? com r-om O0 ,?U1 coo w om O0 1c1 min -0 O0 Y? +I in rl 1 in FI I m l-l I 8 8 OLO O0 O0 NO +I rl I 999990b 2004857 030 MIL-C-48481C (AR) mw cr) om O0 inci. . me CU ow O0 ?U? mm o ocv O0 YU-? wo m 0- O0 m c w* . min PO wo O0 +I Ln rl I m 4 I m rl 1 m rl I 8 Om O0 O0 NO +I
41、 Cu 8 win in o4 04 o.*? eco w O0 o4 o.? dim w 00 O0 .U. m-r LO om O0 ?co. r-Ln mo O0 ?9 +I in rl I m rl I 8 m rl I v) rl I Om O0 NO 99 +I m =ri w ON cvN ,?u* coo P 04 cvcv ?Y mm w om am .Y CJW moco cvcv .U? mm mo WO NO +I m rl I 8 Ln rl I m rl I In rl I om O0 O0 NO +I -r ww -=row O0 ?U,? r-r- m or-
42、O0 ma,? . Ncv r- om O0 YU-7 cv-=r w O0 O0 Y-? mm CU0 e0 O0 +I 8 in rl I in rl I in 4 I in rl I Oin O0 O0 NO +I in . Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-3.3.3 Computer input simulate circuitry. With the loads (items 1.3 through 1.17 of Tab
43、le I), power sources (items 2.2, 2.3, 2.5, and 2.6 of Table I), interconnection (item 4.1 of Table 1) I and input signals (items 3.4, 3.5, and 3.6 of Table I) applied to the assembly; and: (see 4.6.1.3) a. b. C. d. e. With the input signal (item 3.6 of Table I) adjusted to 2.737V rms, and with the p
44、ower sources (items 3.1 and 3.3 of Table I) applied to pin B8 and B1 respectively, the output voltages shall be as specified in Table IV. With the input signal (item 3.6 of Table I) adjusted to 2.585V rms, and with the power sources (items 3.1 and 3.3 of Table I) transferred from pins B8 and B1 to p
45、ins B22 and A25 respectively, the output voltages shall be as specified in Table V. With the input signal (item 3.6 of Table I) adjusted to 2.877V rms, and with the power sources (items 3.1 and 3.3 of Table I) transferred from pins B22 and A25 to pins B24 and A21 respectively, the output voltages sh
46、all be as specified in Table VI. With the input signal (item 3.6 of Table I) adjusted to 2.737V rms, and with the power sources (items 3.1 and 3.3 of Table I) transferred from pins B24 and A21to pins A6 and B4 respectively, the output voltages shall be as specified in Table VII. With the input signa
47、l (item 3.6 of Table I) adjusted to 2.737V rms, and the power sources (items 3.1 and 3.3 of Table I) transferred from pins A6 and B4 to pins B9 and All respectively, the output voltages shall be as specified in Table VIII. Provided by IHSNot for ResaleNo reproduction or networking permitted without
48、license from IHS-,-,-MIL-C-48481C(AR) TABLE IV. Phase 1 outputs. OUTPUT VOLTAGES 1/ ITEM OUTPUT PINS - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B3 A8 B5 B7 A5 B20 A2 O A2 4 A22 Al 9 B26 B25 B19 B2 B23 1.942 + 0.006V rms, Phase 1 0.000 T 0.018V rms 0.000 T 0.018V rms 0.000 0.018V rms 0.000 7 0.015V dc 0.0
49、00 T 0.018V rms 0.000 T 0.018V rms 0.000 7 0.018V rms 0.000 7 0.018V rms 0.000 T 0.015V dc 0.000 T 0.015V dc 0.000 T 0.018V rms 0.000 0.018V rms 0.000 T 0.015V dc 0.000 0.015V dc - i/ Referenced to pin A3. TABLE V. Phase 2 outputs. ITEM OUTPUT PINS OUTPUT VOLTAGES - l/ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B3 A8 B5 B7 A5 B20 A2 O A24 A22 A19 B26 B25 B19 B2 B23 1.835 + 0.006V rms, 1.666 T 0.0
