1、BRITISH STANDARD BS EN 61188-5-1:2002 Printed boards and printed board assemblies Design and use Part 5-1: Attachment (land/joint) considerations Generic requirements The European Standard EN 61188-5-1:2002 has the status of a British Standard ICS 31.180; 31.190 BS EN 61188-5-1:2002 This British Sta
2、ndard was published under the authority of the Standards Policy and Strategy Committee on 1 April 2003 BSI 1 April 2003 ISBN 0 580 41503 1 National foreword This British Standard is the official English language version of EN 61188-5-1:2002. It is identical with IEC 61188-5-1:2002. The UK participat
3、ion in its preparation was entrusted to Technical Committee EPL/501, Electronic assembly technology, which has the responsibility to: A list of organizations represented on this committee can be obtained on request to its secretary. Cross-references The British Standards which implement internationa
4、l or European publications referred to in this document may be found in the BSI Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Search” facility of the BSI Electronic Catalogue or of British Standards Online. This publication does not purport to
5、include all the necessary provisions of a contract. Users are responsible for its correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. aid enquirers to understand the text; present to the responsible international/European committee any e
6、nquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. Summary of pages This document comprises a front cover, an inside front cover, the EN title page, pages 2 to 71 and a ba
7、ck cover. The BSI copyright date displayed in this document indicates when the document was last issued. Amendments issued since publication Amd. No. Date CommentsEUROPEAN STANDARD EN 61188-5-1 NORME EUROPENNE EUROPISCHE NORM October 2002 CENELEC European Committee for Electrotechnical Standardizati
8、on Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2002 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 61188-5-1:2002 E I
9、CS 31.180; 31.190 English version Printed boards and printed board assemblies - Design and use Part 5-1: Attachment (land/joint) considerations - Generic requirements (IEC 61188-5-1:2002) Cartes imprimes et cartes imprimes equipes - Conception et utilisation Partie 5-1: Considrations sur les liaison
10、s pistes-soudures - Prescriptions gnriques (CEI 61188-5-1:2002) Leiterplatten und Flachbaugruppen - Konstruktion und Anwendung Teil 5-1: Betrachtungen zur Montage (Anschluflche/Verbindung) - Allgemeine Anforderungen (IEC 61188-5-1:2002) This European Standard was approved by CENELEC on 2002-10-01. C
11、ENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained o
12、n application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Se
13、cretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands, Norway, Portugal, Slovakia, Spain, Sw
14、eden, Switzerland and United Kingdom.Foreword The text of document 91/292/FDIS, future edition 1 of IEC 61188-5-1, prepared by IEC TC 91, Electronics assembly technology, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61188-5-1 on 2002-10-01. The following dates wer
15、e fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2003-07-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2005-10-01 Annexes designated “normative“ ar
16、e part of the body of the standard. Annexes designated “informative“ are given for information only. In this standard, annex ZA is normative and annexes A and B are informative. Annex ZA has been added by CENELEC. _ Endorsement notice The text of the International Standard IEC 61188-5-1:2002 was app
17、roved by CENELEC as a European Standard without any modification. _ Page2 EN6118851:2002-88116-5 1 IE:C2002 3 CONTENTS 1 Scope and object7 2 Normative references7 3 Terms and definitions.8 4 Design requirements.14 4.1 General.14 4.1.1 Classification.15 4.1.2 Land pattern determination15 4.2 Dimensio
18、ning systems.16 4.2.1 Component tolerancing17 4.2.2 Land tolerancing21 4.2.3 Fabrication allowances.21 4.2.4 Assembly tolerancing.21 4.2.5 Dimension and tolerance analysis 22 4.3 Design producibility30 4.3.1 SMT land pattern.31 4.3.2 Standard component selection.31 4.3.3 Circuit substrate developmen
19、t31 4.3.4 Assembly considerations31 4.3.5 Provision for automated test.31 4.3.6 Documentation for SMT .31 4.4 Environmental constraint.31 4.4.1 Moisture sensitive components 31 4.4.2 End-use environment considerations32 4.5 Design rules33 4.5.1 Component spacing.33 4.5.2 Single- and double-sided boa
20、rd assembly 35 4.5.3 Solder paste stencil .35 4.5.4 Component stand-off height for cleaning 35 4.5.5 Fiducial marks.36 4.5.6 Conductors39 4.5.7 Via guidelines40 4.5.8 Standard fabrication allowances.42 4.5.9 Panelization.44 4.6 Outer layer finishes47 4.6.1 Solder-mask finishes.47 4.6.2 Solder-mask c
21、learances.47 4.6.3 Land-pattern finishes.48 5 Quality and reliability validation .48 5.1 Validation techniques.48 6 Testability.49 6.1 Five types of testing.49 6.1.1 Bare-board test49 6.1.2 Assembled board test 50 Page3 EN6118851:2002-88116-5 1 IE:C2002 4 6.2 Nodal access.50 6.2.1 Test philosophy50
22、6.2.2 Test strategy for bare boards .51 6.3 Full nodal access for assembled board 51 6.3.1 In-circuit test accommodation.52 6.3.2 Multi-probe testing.52 6.4 Limited nodal access.52 6.5 No nodal access53 6.6 Clam-shell fixtures impact53 6.7 Printed board test characteristics.53 6.7.1 Test land patter
23、n spacing.53 6.7.2 Test land size and shape .53 6.7.3 Design for test parameters.54 7 Printed board structure types 55 7.1 General considerations57 7.1.1 Categories.58 7.1.2 Thermal expansion mismatch.58 7.2 Organic base material58 7.3 Non-organic base materials .58 7.4 Alternative PB structures.58
24、7.4.1 Supporting-plane PB structures58 7.4.2 High-density PB technology58 7.4.3 Discrete-wire interconnect59 7.4.4 Constraining core structures 59 7.4.5 Porcelainized metal (metal core) structures59 8 Assembly considerations for surface-mount technology (SMT) 59 8.1 SMT assembly process sequence 59
25、8.2 Substrate preparation60 8.2.1 Adhesive application60 8.2.2 Conductive adhesive61 8.2.3 Solder paste application.61 8.2.4 Solder preforms.61 8.3 Component placement.61 8.3.1 Component data transfer .61 8.4 Soldering processes62 8.4.1 Wave soldering62 8.4.2 Vapour-phase soldering.63 8.4.3 IR reflo
26、w64 8.4.4 Hot air/gas convection .64 8.4.5 Laser reflow soldering64 8.5 Cleaning64 8.6 Repair/rework65 8.6.1 Re-use of removed components.65 8.6.2 Heatsink effects.65 8.6.3 Dependence on printed board material type66 8.6.4 Dependence on copper land and conductor layout66 8.6.5 Selection of suitable
27、rework equipment 66 8.6.6 Dependence on assembly structure and soldering processes .66 Page4 EN6118851:2002-88116-5 1 IE:C2002 5 Annex A (informative) Test patterns Process evaluations.67 Annex B (informative) Abbreviations.70 Annex ZA (normative) Normative references to international publications w
28、ith their corresponding European publications 71 Figure 1 Profile tolerancing method 16 Figure 2 Example of 3216 capacitor dimensioning for optimum solder fillet condition.18 Figure 3 Profile dimensioning of gull-wing leaded SOIC 19 Figure 4 Pitch for multiple leaded component .24 Figure 5 Courtyard
29、 boundary area condition29 Figure 6 Component orientation for wave-solder applications33 Figure 7 Alignment of similar components 34 Figure 8 Panel/local fiducials36 Figure 9 Local and global fiducials37 Figure 10 Fiducial locations on a printed board.37 Figure 11 Fiducial clearance requirements38 F
30、igure 12 Surface mounting geometries .39 Figure 13 Conductor routing capability test pattern .40 Figure 14 Land-pattern-to-via relationship.41 Figure 15 Examples of via positioning concepts41 Figure 16 Conductor description.43 Figure 17 Examples of modified landscapes .44 Figure 18 Typical copper gl
31、ass laminate panel45 Figure 19 Conductor clearance for V-groove scoring.45 Figure 20 Breakaway (routed pattern) with routed slots.46 Figure 21 Routed slots .46 Figure 22 Gang solder mask window 47 Figure 23 Pocket solder mask window48 Figure 24 Component temperature limits 49 Figure 25 Test via grid
32、 concepts.52 Figure 26 General relationship between test contact size and test probe misses .54 Figure 27 Test probe feature distance from component.55 Figure 28 Typical process flow for through-hole/surface-mount assembly60 Figure 29 Typical process flow for full surface-mount type 1b and 2b surfac
33、e-mount technology 60 Figure A.1 General description of process validation contact pattern and interconnect 67 Figure A.2 Photoimage of IPC-A-49 test board for primary side.68 Table 1 Tolerance analysis elements for chip devices.25 Table 2 Flat ribbon L and gull-wing leads (greater than 0,625 mm pit
34、ch) .25 Table 3 Flat ribbon L and gull-wing leads (less than or equal to 0,625 mm pitch).26 Table 4 Round or flattened (coined) leads 26 Table 5 J leads.26 Table 6 Rectangular or square-end components (ceramic capacitors and resistors) 26 Table 7 Cylindrical end cap terminations (MELF) 27 Table 8 Bo
35、ttom only terminations27 Page5 EN6118851:2002-88116-5 1 IE:C2002 6 Table 9 Leadless chip carrier with castellated terminations .27 Table 10 Butt joints 27 Table 11 Inward flat ribbon L and gull-wing leads (tantalum capacitors) 28 Table 12 Flat lug leads .28 Table 13 Worst-case use environments for s
36、urface-mounted electronics and recommended accelerated testing for surface-mount solder attachments by most common use categories 32 Table 14 Conductor width tolerances43 Table 15 Feature location accuracy 43 Table 16 Printed board structure comparison55 Table 17 PB structure selection consideration
37、s.57 Table 18 PB structure material properties.57 Page6 EN6118851:2002-88116-5 1 IE:C2002 7 PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES DESIGN AND USE Part 5-1: Attachment (land/joint) considerations Generic requirements 1 Scope and object This part of IEC 61188 provides information on land pattern
38、geometries used for the surface attachment of electronic components. The intent of the information presented herein is to provide the appropriate size, shape and tolerance of surface-mount land patterns to insure sufficient area for the appropriate solder fillet, and also to allow for inspection, te
39、sting, and rework of those solder joints. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amend
40、ments) applies. IEC 60097, Grid systems for printed circuits IEC 60194, Printed board design, manufacture and assembly Terms and definitions IEC 61188-1-1, Printed boards and printed board assemblies Design and use Part 1-1: Generic requirements Flatness considerations for electronic assemblies IEC
41、61191-1, Printed board assemblies Part 1: Generic specification Requirements for soldered electrical and electronic assemblies using surface mount and related assembly technologies IEC 61191-2, Printed board assemblies Part 2: Sectional specification Requirements for surface mount soldered assemblie
42、s IEC 61192-1, Soldered electronic assemblies Part 1: Workmanship requirements General 1)IEC 61192-2, Soldered electronic assemblies Part 2: Workmanship requirements Surface mounted assemblies 1)IEC 61760-1, Surface mounting technology Part 1: Standard method for the specification of surface mountin
43、g components (SMDs) IEC 62326 (all parts), Printed boards _ 1)To be published. Page7 EN6118851:2002-88116-5 1 IE:C2002 8 3 Terms and definitions For the purposes of this part of IEC 61188, the terms and definitions given in English only in IEC 60194 1)and the following apply. 3.1 assembly number of
44、parts, subassemblies or combinations thereof joined together IEC 60194 3.2 assembly, double-sided packaging and interconnecting structure with components mounted on both the primary and secondary sides 3.3 assembly, multilayer printed circuit (wiring) multilayer printed circuit or printed wiring boa
45、rd on which separately manufactured components and parts have been added 3.4 assembly, packaging and interconnecting (P&IA) generic term for an assembly that has electronic components mounted on either one or both sides of a packaging and interconnecting structure 3.5 assembly, printed board assembl
46、y of several printed circuit assemblies or printed wiring assemblies, or both 3.6 assembly, printed circuit (wiring) printed circuit or printed wiring board on which separately manufactured components and parts have been added 3.7 assembly, single-sided packaging and interconnecting structure with c
47、omponents mounted only on the primary side 3.8 base material insulating material upon which a conductive pattern may be formed (the base material may be rigid or flexible, or both. It may be a dielectric or insulated metal sheet) IEC 60194 3.9 basic dimension numerical value used to describe the the
48、oretical exact location of a feature or hole (it is the basis from which permissible variations are established by tolerance on other dimensions in notes or by feature-control symbols) IEC 60194 _ 1)Certain definitions of IEC 60194 have been translated into French. Page8 EN6118851:2002-88116-5 1 IE:C2002 9 3.10 blind via via extending only to one surface of a printed board IEC 60194 3.11 buried via via that does not extend to the surface of a printed board IEC 60194 3.12 castellation recessed metallized feature on the edge of a leadless chip carri
