1、BRITISH STANDARD BS IEC 60748-23-5: 2003 Incorporating Corrigendum No. 1 Semiconductor devices Integrated circuits Part 23-5: Hybrid integrated circuits and film structures Manufacturing line certification Procedure for qualification approval ICS 31.200 BS IEC 60748-23-5:2003 This British Standard w
2、as published under the authority of the Standards Policy and Strategy Committee on 31 March 2004 BSI 28 April 2004 ISBN 0 580 43614 4 National foreword This British Standard reproduces verbatim IEC 60748-23-5:2003 and implements it as the UK national standard. The UK participation in its preparation
3、 was entrusted by Technical Committee EPL/47, Semiconductors, to Subcommittee EPL/47/1, Film and hybrid integrated circuits, which has the responsibility to: A list of organizations represented on this subcommittee can be obtained on request to its secretary. Cross-references The British Standards w
4、hich implement international or European publications referred to in this document may be found in the BSI Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Search” facility of the BSI Electronic Catalogue or of British Standards Online. This publi
5、cation does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. aid enquirers to understand the text; present to the responsible European co
6、mmittee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. Summary of pages This document comprises a front cover, an inside front cover, the IEC title page, pages 2
7、to 29 and a back cover. The BSI copyright notice displayed in this document indicates when the document was last issued. Amendments issued since publication Amd. No. Date Comments 15162 Corrigendum No. 1 28 April 2004 Correction of identifiersINTERNATIONAL STANDARD IEC 60748-23-5 QC 165000-5 First e
8、dition 2003-10 Semiconductor devices Integrated circuits Part 23-5: Hybrid integrated circuits and film structures Manufacturing line certification Procedure for qualification approval Dispositifs semiconducteurs Circuits intgrs Partie 23-5: Circuits intgrs hybrides et structures par films Certifica
9、tion de la ligne de fabrication Procdure dhomologation Reference number IEC 60748-23-5:2003(E) BSIEC60748235:2003 2 60748-23-5 IEC:2003(E) CONTENTS OFWERODR 3 1 Scope 3 2 Normative references. 3 3 Terms and definitions. 3 4 Qualification approval procedures 3 4.1 General 3 4.2 Marking 3 4.3 Validity
10、 of release for delivery 4 4.4 Application for qualification approval . 4 4.5 Structural similarity . 4 4.6 Materials, piece-parts and added components. 4 4.7 Initial qualification approval. 4 4.8 Granting of qualification approval 5 4.9 Maintenance of qualification approval 5 4.10 Procedure in the
11、event of a failure in a periodic test 6 4.11 Withdrawal of qualification approval 6 5 Qualification-product assessment level schedules 7 6 Blank detail specification.26 6.1 General .26 6.2 FRONT PAGE FOR COMPONENTS ASSESSED BY QUALIFICATION APPROVAL27 6.3 GENERAL DATA28 6.4 Inspection requirements.2
12、9 BSIEC60748235:2003 1 BSIEC60748235:2003 1 EN60748235:2003SB 2 BS3002:53294706CEIBSIEC60748235:2003260748-23-5 IEC:2003(E) 5 SEMICONDUCTOR DEVICES INTEGRATED CIRCUITS Part 23-5: Hybrid integrated circuits and film structures Manufacturing line certification Procedure for qualification approval 1 Sc
13、ope This part of IEC 60748-23 applies to high quality hybrids (with films) incorporating special customer quality and reliability requirements whose quality is assessed on the basis of Qualification Approval. NOTE 1 Hybrid integrated circuits may be fully or part completed. Part completed devices ar
14、e those that may be supplied to customers for further processing. NOTE 2 Test methods are selected from IEC 60748-23-1. A blank detail specification (BDS) is included to assist manufacturers and users in the preparation of detail specifications. 2 Normative references The following referenced docume
15、nts are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 60748-23-1:2002, Semiconductor devices Integrated circuits Part 23-1: Hybrid
16、 integrated circuits and film structures Manufacturing line certification Generic specification IEC 61340-5-1:1998, Electrostatics Part 5-1: Protection of electronic devices from electro- static phenomena General requirements QC 001002-3:1998, IEC Quality Assessment System for Electronic Components
17、(IECQ) Rules of Procedure Part 3: Approval procedures 3 Terms and definitions For the purposes of this part of IEC 60748, related documents, preferred ratings and characteristics, and terminology are given in IEC 60748-23-1. 4 Qualification approval procedures 4.1 General The procedures in QC 001002
18、-3 shall apply. Subclause 6.1 of IEC 60748-23-1 applies with the exceptions given in 4.2 to 4.11 of this standard. 4.2 Marking Clause 5 of IEC 60748-23-1 applies. BSIEC60748235:20032 BSIEC60748235:20032 3002:53284706BSEN3 94706CEISB235:2003BSIEC60748235:20033 6 60748-23-5 IEC:2003(E) 4.3 Validity of
19、 release for delivery Circuits may be released under qualification approval subject to the following conditions: a) the circuits conform with the requirements of the detail specification; b) the circuits, their added components, piece parts and materials are traceable to original manufacturers lot n
20、umbers. 4.4 Application for qualification approval Application shall be made to the NSI in accordance with QC 001002-3. In addition, the manufacturer shall: a) conform with the eligibility requirements of 6.1.1 of IEC 60748-23-1; b) conform with the relevant detail specification based on the blank d
21、etail specification (see Clause 6) and the Qualification product assessment level schedules (Q-PALS) (see Clause 5) contained in this standard. 4.5 Structural similarity For the purposes of assessment testing, structural similarity can be used if the testing of one representative type of circuit giv
22、es at least the same quality level for the rest of the types which are grouped together. The designated management representative (DMR) shall declare to the satisfaction of the NSI the method of operating the structural similarity plan within the manufacturing facilities and agree the representative
23、 type(s) from each structurally similar group. For the qualification approval procedure, two or more circuits can be considered structurally similar, and thus the required numbers of specimens for a test shall be selected from the combined production, when they have the same function type, use the s
24、ame design rules, materials, processes and methods (for example a range of T-cell thick film attenuators using the same line of inks; or thin film D/A convertors using the same film material and same added components from the same supplier). Only those tests not specifically excluded in the Q-PALS m
25、ay be considered for structural similarity. 4.6 Materials, piece-parts and added components Subclause 6.1.3 of IEC 60748-23-1 applies. 4.7 Initial qualification approval The schedules to be used for qualification approval testing on the basis of lot-by-lot and periodic testing are given in the Q-PAL
26、S tables contained in this standard. The procedure for initial qualification approval is given below. The relevant Q-PALS for initial qualification approval, release of products (lot-by-lot tests) and maintenance of qualification approval (periodic tests) collectively prescribe the minimum test prog
27、ramme on completed circuits. 1) Sampling The sample shall be representative of the range of circuits for which approval is sought (see 6.4.3 of IEC 60748-23-1). The size of the sample and the criterion of acceptability depend on the relevant Q-PALS which it is intended to release against. BSIEC60748
28、235:20033 BSIEC60748235:20033 EN60748235:2003SB4 BS3002:53294706CEIBSIEC60748235:2003460748-23-5 IEC:2003(E) 7 2) Tests The complete series of tests specified in the relevant Q-PALS contained in this standard is required for the approval of circuits covered by one detail specification. The tests sha
29、ll be carried out in the order given. Test and measurement procedures are given in Clause 7 of IEC 60748-23-1. Samples used for Group B, C and D tests shall have passed Group A tests. One failure is counted when a circuit has not satisfied the whole, or a part, of the tests of a group. Approval is g
30、ranted when the number of failures does not exceed the specified number of permissible failures for each group or sub-group. 4.8 Granting of qualification approval The manufacturer shall submit a report to the NSI covering the qualification approval testing in accordance with the requirements of 4.7
31、 of this standard, and with QC 001002-3. Qualification approval shall be granted when the requirements of this standard have been satisfied. A qualification approval certificate will be issued by the responsible national authority in accordance with QC 001002-3. 4.9 Maintenance of qualification appr
32、oval 4.9.1 General Qualification approval is maintained after successful completion of the procedures and requirements of quality conformance inspection (see 6.4.2 of IEC 60748-23-1) with the following details: 1) Design evaluation tests In addition to the initial delivery lot, design evaluation tes
33、ts shall be carried out at the periodicity specified in the detail specification. 2) Detail specification The detail specification shall conform to the requirements of the BDS and Q-PALS in this standard. The manufacturer shall also have maintained continuous production, for example: a) no change ha
34、s occurred in the place of manufacture and final test; b) no break exceeding two years has occurred in the manufacturers declared periodic test schedule. 4.9.2 Changes to qualification approval The manufacturer is required to notify the NSI of changes to his qualification approval in accordance with
35、 QC 001002-3 and 6.5.2 of IEC 60748-23-1, where applicable. NOTE All re-verification programmes are to be agreed with the NSI. BSIEC60748235:20034 BSIEC60748235:20034 3002:53284706BSEN5 94706CEISB235:2003BSIEC60748235:20035 8 60748-23-5 IEC:2003(E) 4.10 Procedure in the event of a failure in a perio
36、dic test The procedure described in QC 001002-3 shall apply. 4.11 Withdrawal of qualification approval The procedures in QC 001002-3 shall apply. BSIEC60748235:20035 BSIEC60748235:20035 EN60748235:2003SB6 BS3002:53294706CEIBSIEC60748235:2003660748-23-5 IEC:2003(E) 9 5 Qualification-product assessmen
37、t level schedules NOTE The following 11 Q-PALS are based upon corresponding PALS in IEC 60748-23-1, Annex A. Q-PRODUCT ASSESSMENT LEVEL SCHEDULE 1 Applicability This assessment schedule is intended for use with solder assembled and/or bare die, non- hermetic encapsulated, unencapsulated, cavity or n
38、on-cavity devices, which are for use in benign mechanical and temperature environments. _ Subgroup A tests: Device screening 100 % IEC 60748-23-1 Reference 1. Electrical test at T amb . Those tests in the detail specification which define circuit functionality 7.4 _ Subgroup B tests (lot-by-lot): De
39、vice sample testing IL S4 AQL 0,4 % 1. Electrical test at T amb(other than those specified for screening) 7.4 2. External visual inspections 7.3.2 _ Subgroup C tests (6 monthly period): Design evaluation Minimum sample 8. Accept on 0 failures. 1. Electrical test. All specified parameters at T minand
40、 T max * 7.4 2. Dimensions 7.3.3 _ Subgroup D tests (12 monthly period): Design evaluation Minimum sample 3. Accept on 0 failures. 1. Resistance of circuits to solder heat (D) 7.5.11 2. Solderability (ND/D) 7.5.10 3. Robustness of terminations (D) 7.5.12 4. Flammability (D) 7.5.16 5. Resistance to s
41、olvents (ND) 7.5.15 _ Process and packaging requirements 1. Substrate fabrication = class 100 000. 2. Substrate assembly (bare die) = class 100 000. 3. ESD precautions (where applicable) to IEC 61340-5-1. 4. Pre-cap visual at IL S4 AQL 0,4 % minimum. 7.3.1 _ * Structural similarity rules do not appl
42、y. BSIEC60748235:20036 BSIEC60748235:20036 3002:53284706BSEN7 94706CEISB235:2003BSIEC60748235:20037 10 60748-23-5 IEC:2003(E) Q-PRODUCT ASSESSMENT LEVEL SCHEDULE 2 Applicability This assessment schedule is intended for use with solder assembled and/or bare die, non-hermetic encapsulated, unencapsula
43、ted, cavity or non-cavity devices, which are for use in benign mechanical and temperature environments. _ Subgroup A tests: Device screening 100 % IEC 60748-23-1 Reference 1. Electrical test at T amb . Those tests in the detail specification which define circuit functionality 7.4 _ Subgroup B tests
44、(lot-by-lot): Device sample testing IL S4 AQL 0,4 % 1. Electrical test at T amb(other than those specified for screening) 7.4 2. External visual inspection 7.3.2 _ Subgroup C tests (6 monthly period): Design evaluation Minimum sample 8. Accept on 0 failures 1. Electrical endurance 1 000 h. Release a
45、fter 160 h * 7.5.14 2. Electrical test. All specified parameters at T minand T max * 7.4 3. Dimensions 7.3.3 _ Subgroup D tests (12 monthly period): Design evaluation Minimum sample 3. Accept on 0 failures 1. Resistance of circuits to solder heat (D) 7.5.11 2. Solderability (ND/D) 7.5.10 3. Robustne
46、ss of terminations (D) 7.5.12 4. Flammability (D) 7.5.16 5. Resistance to solvents (ND) 7.5.15 _ Process and packaging requirements 1. Substrate fabrication = class 100 000. 2. Substrate assembly (bare die) = class 100 000. 3. ESD precautions (where applicable) to IEC 61340-5-1. 4. Pre-cap visual at IL S4 AQL 0,4 % minimum. 7.3.1 _ * Structural similarity rules do not apply. BSIEC60748235:20037 BSIEC60748235:20037 EN60748235:2003SB8 BS3002:53294706CEIBSIEC60748235:2003860748-23-5 IEC:2
