1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Origina
2、l date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, DIGITAL DUAL SYNCHRONOUS BUCK POWER DRIVER, MONOLITHIC SILICON 13-11-12 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/14601 REV PAGE 1 OF 12 AMSC N/A 5962-V014-14 Provided by IHSNot for Resa
3、leNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance digital dual synchronous buck power driver mi
4、crocircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation
5、: V62/14601 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 UCD7242-EP Digital dual synchronous buck power driver 1.2.2 Case outline(s). The case outlines are as specified herein. Outline l
6、etter Number of pins Package style X 32 Plastic quad flatpack No-lead 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash pallad
7、ium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage, (VIN) -0.3 V to 20.0 V Boot voltage, (BST): DC
8、-0.3 V to SW + 7.0 V AC 34 V 2/ Gate supply voltage, (VGG, VGG_DIS) 7 V Logic supply voltage, (BP3) 4 V Switch voltage, (SW, BSW): DC -2.0 V to VIN + 1.0 V AC 34 V 2/ Analog outputs, (TMON, IMON, Testmode) -0.3 V to 3.6 V Digital I/Os, (PWM-A, PWM-B, SRE-A, SRE-B, FLT-A, FLT-B) . -0.3 V to 5.5 V Jun
9、ction temperature, (TJ) . -55C to 150C Storage temperature range, (Tstg) . -55C to 150C ESD rating: HBM: Human Body model 2000 V CDM: Charged device model . 500 V 1.4 Thermal characteristics. Thermal metric 3/ Case outline X Units Junction to ambient thermal resistance, JA4/ 40.7 C/W Junction to cas
10、e (top) thermal resistance, JCtop5/ 17.8 Junction to board thermal resistance, JB6/ 12 Junction to top characterization parameter, JT7/ 0.1 Junction to board characterization parameter, JB8/ 11.9 Junction to case (bottom) thermal resistance, JCbot9/ 0.3 1/ Stresses beyond those listed under “absolut
11、e maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extend
12、ed periods may affect device reliability. 2/ AC levels are limited to within 5 ns. 3/ For more information about traditional and new thermal metrics, see manufacturer data. 4/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-
13、board, as specified in JESD51-7, in an environment described in JESD51-2a. 5/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
14、 6/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 7/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and
15、 is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ The junction to board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, u
16、sing a procedure described in JESD51-2a (sections 6 and 7). 9/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Prov
17、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 4 1.5 Recommended operating conditions. Power input voltage, VIN(internally generated VGG) . 4.75 V to 18.0 V Powe
18、r input voltage, VIN(externally generated VGG) 2.20 V to 18.0 V Externally supplied gate drive voltage, VGG. 4.75 V minimum Operating junction temperature range, TJ. -55C to 125C Switching frequency, fS. 300 kHz to 2000 kHz 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JES
19、D51 Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device). JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8
20、Integrated Circuits Thermal Test Method Environment Conditions Junction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITU
21、TE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6
22、 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (
23、optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4,
24、and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be a
25、s shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Block diagram. The block diagram shall be as shown in figure 4. 3.5.5 Sensed current variability. The Sensed current variability shall be as shown in figure 5. Provided by IHSNot for ResaleNo rep
26、roduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max Supply section Supply current Output
27、s not switching, VIN= 2.2 V, PWM(INH) = LOW, SRE(INL) = HIGH, VGG_DIS = HIGH, VGG= 5V 6 mA Outputs not switching, VIN = 18 V, PWM(INH) = LOW, SRE(INL) = HIGH, VGG_DIS = LOW 6 GATE DRIVE UNDER VOLTAGE LOCKOUT UVLO On VGGBP3 rising 4.0 V UVLO Off BP3 falling 3.8 UVLO hysteresis 200 mV VGGSUPPLY GENERA
28、TOR VGGVIN= 7 to 18 V 5.2 6.25 6.8 V VGGdrop out VIN= 4.75 to 7 V, IGG 50 mA 850 mV BP3 supply voltage BP3 IDD= 0 to 10 mA 3.15 3.3 3.45 V Input signal (PWM, SRE) Positive going input threshold voltage VIH2.1 2.3 V Negative going input threshold voltage VIL1 1.2 3-state condition 1.4 1.9 3-state hol
29、d off time tHLD_RVPWM= 1.65 V 275 ns Input current IPWMVPWM= 5.0 V 133 A VPWM= 3.3 V 66 VPWM= 0 V -66 Input current ISREVSRE= 5.0 V 1 VSRE= 3.3 V 1 VSRE= 0 V 1 VGGdisable (VGG_DIS) Input resistance to AGND VGG_DIS 45 100 150 k Threshold 1.35 1.6 V Hysteresis 550 mV Fault Flag (FLT) FLT output high l
30、evel IOH= 2 mA 2.7 V FLT output low level IOL= -2 mA 0.6 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 6 TABLE I. Electrical p
31、erformance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max Current limit Over current threshold 12 15 18.5 A Tfault_HSdelay until HS FET off 3/ 80 ns Tfault_FFdelay until FLT asserted 3/ 100 Propagation delay from PWM to reset FLT 3/ 1stfalling edge of PWM with
32、out a fault event 100 High side blanking time 3/ Over currents during this period will not be detected 60 Current sense amplifier Gain IMON/IOUT, see FIGURE 5 17 20 26 A/A Bandwidth 3/ 5 kHz Thermal sense Thermal shutdown 3/ 170 C Thermal shutdown hysteresis 3/ 20 Temperature sense T 3/ Gain TJ = -2
33、0C to 125C 10 mV/C Temperature sense T offset 3/ TJ= 0C, -100 A ITMON 100 A 470 mV Power MOSFETS Propagation delay from PWM to switch node going high 32 ns High side MOSFET RDS(ON)15.5 m Low side MOSFET RDS(ON)6.5 High side MOSFET turn on Dead time 3/ 5 10 ns Low side MOSFET turn on Dead time 3/ 6 1
34、1 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of sp
35、ecific parametric testing, product performance is assured by characterization and/or design. 2/ VIN= 12V; 1F from BP3 to GND, 0.22F from BST to BSW, 4.7F from VGGto PGND, TA= TJ= 55C to 125C (unless otherwise noted). 3/ As designed and characterized. Not 100% tested in production. These specificatio
36、ns apply for 40C TJ 125C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 7 Case X Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 0.80 1.0
37、0 D/E 5.85 6.15 A1 0.00 0.05 e 0.50 BSC A2 0.20 REF e1 4.00 BSC b 0.25 0.35 e2 0.25 TYP b1 0.35 TYP e3 0.50 TYP b2 0.35 TYP L 0.30 0.50 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Quad Flatpack, No-Lead (QFN) package configuration. 4. T
38、he package thermal pad must be soldered to the board for thermal and mechanical performance. 5. See the addition figure in the production data sheet from manufacturer for details regarding the exposed thermal pad features and dimensions. FIGURE 1. Case outline. DEPIN 1 INDEX AREATOP AND BOTTOMA0.08
39、A1A2CSEATINGPLANEe11 9b14 PLS10e28 PLS11121314151617e34 PLSeBC A0.10 M0.05 M C182627b24 PLSb22 PLS2829303132L22 PLSABANCHOR PADS4 PLS(TO BE SOLDERED)Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDEN
40、T NO. 16236 DWG NO. V62/14601 REV PAGE 8 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 PWM_B 32 VIN2 SRE_B 31 NC 3 BST_B 30 VIN4 BSW_B 29 VIN5 VGG28 NC 6 VGG_DIS 27 VIN7 IMON_B 26 PWM_A 8 testmode 25 SRE_A 9 FLT_B 24 BST_A 10 PGND 23 BSW_A 11 NC 22 BP3 12 PGND 21 A
41、GND 13 SWB 20 IMON_A 14 SWA 19 TMON 15 PGND 18 FLT_A 16 NC 17 PGND FIGURE 2. Terminal connections. Case outline X Terminal number Terminal symbol I/O Function 1 PWM_B I High impedance digital input capable of accepting 3.3V or 5 V logic level signals up to 2 MHz. A Schmitt trigger input comparator d
42、esensitizes this pin from external noise. This pin controls the state of the high side MOSFET and the low side MOSFET when SRE-B is high. PWM = high PWM = low PWM = 1.65 V SRE = high HS = on, LS = off HS = off, LS = on HS = off, LS = off SRE = low HS = on, LS = off HS = off, LS = off HS = off, LS =
43、off 2 SRE_B I Synchronous Rectifier Enable input for the B-channel. High impedance digital input capable of accepting 3.3V or 5V logic level signals used to control the synchronous rectifier switch. An appropriate anti-cross-conduction delay is used during synchronous mode. 3 BST_B I Connection for
44、the B-channel charge pump capacitor that provides a floating supply for the high side driver. Connect a 0.22F ceramic capacitor from this pin to BSW-B (pin 4). 4 BSW_B I Connection for B-channel charge pump capacitor. Internally connected to SW-B. 5 VGGI/O Gate drive voltage for the power MOSFETs. F
45、or VIN 4.75V, the internal VGG generator can be used. For VIN 4.75 V, this pin should be driven from an external bias supply. When externally driven, VGG_DIS must be tied to VGG. In all cases, bypass this pin with a 4.7F (min), 10V (min) ceramic capacitor to PGND. FIGURE 3. Terminal function. Provid
46、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14601 REV PAGE 9 Case outline X Terminal number Terminal symbol I/O Function 6 VGG_DIS I When tied to VGG, disables the on-chip VGG
47、 generator to allow gate drive voltage to be supplied from an external source. This is required when VIN is 4.75V. To use the internal VGG generator, tie to GND. 7 IMON_B O MOSFET current sense monitor output. Provides a current source output that is proportional to the current flowing in the power
48、MOSFETs. The gain on this pin is equal to 20A/A. The IMON pin should be connected to a resistor to GND to produce a voltage proportional to the power-stage load current. 8 testmode I Test mode only. Tie to GND. 9 FLT_B O Fault flag for the B-channel. This signal is a 3.3V digital output which is latched high when the current in the B
