1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 11-04-19 David J. Corbett CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE
2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-V ABT 16-BIT
3、BUFFER/DRIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-04-21 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04707 REV A PAGE 1 OF 11 AMSC N/A 5962-V041-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPL
4、Y CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT 16-bit buffer/driver with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C
5、. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04707 - 01 X E Drawing Device type Case outline Lead finis
6、h number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH162240-EP 3.3-V ABT 16-bit buffer/driver with 3-state outputs 1.2.2 Case outline. The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48
7、 MO-153 Plastic small-outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo
8、reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltag
9、e range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state (VO) . -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO) . 30 mA Current into any output in the high state (IO) . 30 mA 3/ Input cl
10、amp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Package thermal impedance (JA) . 89C/W 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ 6/ Supply voltage range (VCC) . 2.7 V to 3.6 V Minimum high level input voltage (VIH) 2.0 V Ma
11、ximum low level input voltage (VIL) . 0.8 V Maximum input voltage (VI) . 5.5 V Maximum high level output current (IOH) . -12 mA Maximum low level output current (IOL) . 12 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Minimum power-up ramp rate (t/VCC) 200 s/V Operati
12、ng free-air temperature range (TA) -40C to +85C 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
13、operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ This current flows only when the out
14、put is in the high state and VO VCC. 4/ The package thermal impedance is calculated in accordance with JESD 51. 5/ All unused control inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers design rules or stated parameters is
15、 done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE
16、 IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 4 2. APPLICABLE DOCUMENTS ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these doc
17、uments are available online at http:/www.eia.org or from the Electronic Industries Alliance, Technology Strategy & Standards Department, 2500 Wilson Boulevard, Arlington, VA 22201.) (Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA
18、 22201-3834 or at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit contain
19、er. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 De
20、sign, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. Th
21、e logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking
22、permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIKII= -18
23、 mA 2.7 V 25C, -40C to 85C All -1.2 V High level output voltage VOHIOH= -12 mA 3 V 2 V Low level output voltage VOLIOL= 12 mA 3 V 0.8 V Input current IIVI= 5.5 V 0 V or 3.6 V 10 A Control inputs. VI= VCCor GND 3.6 V 1 Data inputs. VI= VCC1 Data inputs. VI= 0 V -5 Input/output power-off leakage curre
24、nt IoffVIor VO= 0 to 4.5 V 0 V 100 A Input current (hold) II(hold)Data inputs. VI= 0.8 V 3 V 75 AData inputs. VI= 2 V -75 Data inputs. VI= 0 V to 3.6 V 3.6 V 2/ +500 -750 3-state output current high IOZHVO= 3 V 3.6 V 5 A 3-state output current low IOZLVO= 0.5 V 3.6 V -5 A 3-state output current powe
25、r-up IOZPUVO= 0.5 V to 3 V OE = dont care 0 V to 1.5 V 100 A 3-state output current power-down IOZPDVO= 0.5 V to 3 V OE = dont care 1.5 V to 0 V 100 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTE
26、R, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Quiescent supply current ICCOutputs high. VI= VCCor GND IO= 0 A 3.6 V 25C, -40C
27、to 85C All 0.19 mA Outputs low. VI= VCCor GND IO= 0 A 5 Outputs disabled. VI= VCCor GND IO= 0 A 0.19 Quiescent supply current delta ICC3/ One input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.2 mA Input capacitance CiVI= 3 V or 0 V 3.3 V 25C 4 TYP pF Output capacitance CoVO= 3 V or 0 V 9
28、TYP pF Propagation delay time, A to Y tPLHCL= 50 pF See figure 5. 2.7 V 25C, -40C to 85C 4.6 ns 3.3 V 0.3 V 1 4 tPHL2.7 V 4.63.3 V 0.3 V 1 4 Propagation delay time, output enable, OE to Y tPZH2.7 V 5.7 ns 3.3 V 0.3 V 1 4.8 tPZL2.7 V 4.93.3 V 0.3 V 1 4.7 Propagation delay time, output disable, OE to
29、Y tPHZ2.7 V 5.2 ns 3.3 V 0.3 V 2 4.7 tPLZ2.7 V 4.53.3 V 0.3 V 2 4.5 Output skew tsk(o)CL= 50 pF 2.7 V 0.5 ns 3.3 V 0.3 V 0.5 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not nec
30、essarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This is the bus-hold maximum dynamic current. It is the minimum overdrive current
31、 required to switch the input from one state to another. 3/ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCCor GND. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER
32、, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - .047 E1 6.00 6.20 .236 .244 A1 0.05 0.15 .002 .006 e 0.50 BSC .020 BSC b 0.17 0.27 .007 .011 L 0.50 0.
33、75 .020 .030 D 12.40 12.60 .488 .496 L1 0.25 TYP .010 TYP E 7.90 8.30 .311 .327 L2 0.15 NOM .006 NOM NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 m
34、illimeters (0.006 in). 4. Fall within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 8 (each 4-bit buffer)
35、Inputs Output OE A Y L L H H L X L H Z H = High voltage level L = Low voltage level X = Immaterial Z = High-impedance state FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBU
36、S COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 1OE 25 3OE 2 1Y1 26 4A4 3 1Y2 27 4A34 GND 28 GND 5 1Y3 29 4A2 6 1Y4 30 4A17 VCC31 VCC8 2Y1 32 3A49 2Y2 33 3A3 10 GND 34 GND 11 2
37、Y3 35 3A2 12 2Y4 36 3A113 3Y1 37 2A4 14 3Y2 38 2A315 GND 39 GND 16 3Y3 40 2A2 17 3Y4 41 2A118 VCC42 VCC19 4Y1 43 1A4 20 4Y2 44 1A321 GND 45 GND 22 4Y3 46 1A2 23 4Y4 47 1A124 4OE 48 2OE FIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without licens
38、e from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 10 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Wa
39、veform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, and tf 2.5 ns. 4. The outputs are measured one at a time wi
40、th one input transition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04707 REV A PAGE 11 4. VERIFI
41、CATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of m
42、oisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic
43、discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified
44、 as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufactu
45、rer CAGE code Vendor part number Top side marking V62/04707-01XE 01295 CLVTH162240IDGGREP LH162240EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
