1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of
2、drawing CHECKED BY Phu H. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, IEEE-1394 LINK LAYER CONTROLLER, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/08625 YY MM DD 08-06-24 REV PAGE 1 OF 17 AMSC N/A 5962-V051-08 .Provided by IHSNot for ResaleNo reproduction or networ
3、king permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08625 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance IEEE-1394 Link Layer controller microcircuit, with an extended
4、 operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/08625 - 01 X
5、E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TSB12LV21B-EP IEEE-1394 Link layer Controller 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC
6、PUB 95 Package style X 176 JEDEC MO-136 Plastic quad flat pack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Ot
7、her 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range: VCC-0.5 V to +4.0 V VCCP-0.5 V to +6.0 V VCC5V. -0.5 V to +6.0 V Input voltage range for Universal PCI, (VI) . -0.5 V to VCCP+0.5 V Input voltage range for 5 V tolerant TTL/LVCMOS, (VI) . -0.5 V to VCCP+0.5 V Output voltage range for Univ
8、ersal PCI, (VO) . -0.5 V to VCCP+0.5 V Output voltage range for 5 V tolerant TTL/LVCMOSI, (VO) -0.5 V to VCC5V+0.5 V Input clamp current (VIVCC) (IIK) 20 mA 3/ Output clamp current (VOVCC) (IOK) . 20 mA 4/ _ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage t
9、o the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Lo
10、ng term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See manufacturer data for more information on enhanced plastic package. 3/ Applies to external input and bidirectional buffers. For 5 V tolerant buffers,
11、 use VI VCC5V. For Universal PCI, use VI VCCP. 4/ Applies to external output and bidirectional buffers. For 5 V tolerant buffers, use VO VCC5V. For Universal PCI, use VO VCCP. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COL
12、UMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08625 REV PAGE 3 1.4 Recommended operating conditions. 5/ Core voltage (VCC) +3.0 V to +3.6 V I/O voltage (VCCP) . +3.0 V to +5.5 V I/O voltage (VCC5V) +3.0 V to +5.5 V Minimum high level input voltage (VIH) . 2.0 V 6/ Maximum low level in
13、put voltage (VIL) 0.8 V 6/ Input voltage: Universal PCI (VI) . 0.0 V to VCCP5 V tolerant (VI) . 0.0 V to VCC5VOutput voltage, (VO) . 0.0 V to VCC7/ Input transition times (trand tf) . 0 ns to 6 ns Operating free-air temperature range ( TA). -55C to +125C Virtual junction temperature (Commercial and
14、industrial) . 0C to +115C 8/ 2. APPLICABLE DOCUMENTS IEEE Standard 1394a - IEEE Standard for Higher Performance Serial Buses Allowing Gigabit Signaling. (Applications for copies should be addressed to the Institute of Electrical and Electronic Engineers, 445 Hoes Lane, Piscataway, NJ 08854-4150 JEDE
15、C PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked
16、with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) a
17、bove. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 5/ Unused or floating pin (input or I/O) must be held high or low. 6/ Applies for external input and bidirectional buffe
18、rs without hysteresis. 7/ Applies for external output buffers. 8/ These junction temperatures reflect simulation conditions. Customer is responsible for verifying the junction temperature. Absolute maximum junction temperature is 150C. Provided by IHSNot for ResaleNo reproduction or networking permi
19、tted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08625 REV PAGE 4 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s).
20、The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 PCI interface timing waveforms. The PCI interface timing waveforms shall be
21、 as specified in figure 4. 3.5.5 Phy_Link interface timing waveforms. The Phy_Link interface timing waveforms shall be as specified in figure 5. 3.5.6 Local bus timing waveforms. The local bus timing waveforms shall be as specified in figure 6. 3.5.7 Zoom Video IF timing waveforms (8 bit, divide-by-
22、2 mode). The Zoom Video IF timing waveforms (8 bit, divide-by-2 mode) shall be as specified in figure 7. 3.5.8 Zoom Video IF timing waveforms (16 bit, divide-by-1 mode). The Zoom Video IF timing waveforms (16 bit, divide-by-1 mode) shall be as specified in figure 8. 3.5.9 Zoom Video IF timing wavefo
23、rms (16 bit, divide-by-2 mode). The Zoom Video IF timing waveforms (16 bit, divide-by-2 mode) shall be as specified in figure 9. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 1623
24、6 DWG NO. V62/08625 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Test 1/ Symbol Operation Test condition 2/ unless otherwise noted Min Max Unit 3.3 V IOH= -0.5 mA 0.9 VCCPCI 5 V IOH= -2 mA 2.4 TTL/LVCMOS 4/ IOH= -18 mA 2.4 High level output voltage 3/ TTL/LVCMOS 4/ VOHIOH= -
25、14 mA 2.4 V 3.3 V IOL= 1.5 mA 0.1 VCCPCI 5 V IOL= 6 mA 0.5 TTL/LVCMOS 5/ IOL= 18 mA 0.5 Low level output voltage TTL/LVCMOS 5/ VOLIOL= 14 mA 0.5 V Bushold VI= 0.8 V 20 Input pins Others VI= GND -1 Bushold VI= 0.8 V 400 Low level input current I/O pins Others IILVI= GND -20 A Bushold VI= 2 V -20 Inpu
26、t pins Others VI= 5.5 V 20 Bushold VI= 2 V -20 High level input current I/O pins Others IIHVI= 5.5 V 20 A Limits Test Symbol Measured Test condition 2/ unless otherwise noted Min Max Unit PCI interface switching characteristics (See figure 4) Setup time, pci_xx low or high to pci_clk high 6/ tsu140%
27、 to 40% 7 Hold time, pci_clk high to pci_xx low or high, gnt_pci low or high 6/ th140% to 40% 0 Delay time, pci_clk high to pci_xx low or high 6/ td140% to 40% 2 11 Setup time, gnt_pci low or high to pci_clk high tsu240% to 40% 10 Delay time, pci_clk high to aint_pci low or high td240% to 40% 2 13 n
28、s See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08625 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Limits
29、Test Symbol Measured Test condition 2/ unless otherwise noted Min Max Unit PHY-LINK interface switching characteristics (See figure 5) Setup time, phy_xx low or high to phy_clk high 7/ tsu31.3 V to 1.3 V 4 Hold time, phy_clk high to phy_xx, link_cyclein low or high th21.3 V to 1.3 V 1 Delay time, ph
30、y_clk high to phy_xx, phy_Ireq low or high 7/ td31.3 V to 1.3 V 3 11 Setup time, phy_clk high to link_cyclein low or high tsu41.3 V to 1.3 V 5 Delay time, phy_clk high to link_cycleout low or high td41.3 V to 1.3 V 3 13 ns Local bus switching characteristics (See figure 6) Delay time, aux_clk high t
31、o aux_adr, aux_data 15-0 (write), oe_aux valid 8/ td51.3 V to 1.3 V 0 15 Delay time, aux_clk high to cs_rom , cs_ram , cs_aux valid td61.3 V to 1.3 V 0 20 Delay time, 0we_aux , 1we_aux high (deasserted) to aux_adr, aux_data15-0 (write), oe_aux , cs_rom , cs_ram , cs_aux valid td71.3 V to 1.3 V 0.5 D
32、elay time, aux_clk low to 0we_aux , 1we_aux low (asserted) td81.3 V to 1.3 V 0 10 Delay time, aux_clk high to 0we_aux , 1we_aux high (deasserted) td91.3 V to 1.3 V 0 10 Delay time, aux_clk high to gpio_data3-0 valid td101.3 V to 1.3 V 2 15 Setup time, aux_adr, adr_data15-0 (write), oe_aux , cs_rom ,
33、 cs_ram , cs_aux valid before 0we_aux , 1we_aux low (asserted) tsu51.3 V to 1.3 V 5 Setup time, aux_data15-0 (read), rdy_aux , gpio_data3-0 valid before aux_clk high tsu61.3 V to 1.3 V 10 Hold time, aux_data15-0 (read), rdy_aux , gpio_data3-1 invalid after aux_clk high th31.3 V to 1.3 V 0 ns See not
34、es at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08625 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Limits Test Symb
35、ol Measured Test condition 2/ unless otherwise noted Min Max Unit Zoom video port switching characteristics, source clock = 30 ns with a 50% duty cycle Setup time, zv_vsync, zv_data_valid high before zv_pix_clk high tsu71.3 V to 1.3 V 12 Hold time, zv_hsync high zv_vsync, zv_data_valid low after zv_
36、pix_clk low th41.3 V to 1.3 V 14 Setup time, aux_data7-0 valid before zv_pix_clk high or low tsu81.3 V to 1.3 V 10 Hold time, aux_data7-0 valid after zv_pix_clk high or low th51.3 V to 1.3 V See figure 4 14 Delay time, zv_hsync low, zv_vsync, zv_data_valid high after zv_pix_clk low td111.3 V to 1.3
37、V -1 3 Delay time, aux_data7-0 invalid after zv_pix_clk low td121.3 V to 1.3 V See figure 5 -1 5 Setup time, zv_hsync low before zv_pix_clk high tsu91.3 V to 1.3 V 25 Hold time, zv_hsync high after zv_pix_clk high th61.3 V to 1.3 V 14 Setup time, zv_vsync low before zv_pix_clk high tsu101.3 V to 1.3
38、 V 10 Setup time, aux_data7-0 valid, zv_data_valid high before zv_pix_clk high tsu111.3 V to 1.3 V 25 Hold time, aux_data7-0 valid, zv_data_valid low after zv_pix_clk high th71.3 V to 1.3 V See figure 6 14 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to
39、assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design.
40、2/ Over recommended operating conditions, unless otherwise noted. 3/ VOH is not tested on serr_pci (31) or aint_pci (166) due to open-drain output. 4/ All PHY-link pins, aux_clk(64), 1we_aux (71), and 0we_aux (73). 5/ All other TTL/VCMOS pins. 6/ In this case, pci_xx refers to the following signals;
41、 pci_ad31-0, , pci_par, frame_pci , irdy_pci , trdy_pci , devsel_pci , stop_pci , idsel_pci , perr_pci , serr_pci , req_pci . 7/ In this case, phy_xx refers to the following bidirectional signals; phy_ctl1-0, phy_data7-0. 8/ These signals are asserted asynchronously when a ZOOM port transfer immedia
42、tely preceeds the local bus transfer. In all cases, the setup time to aux_we1 and aux_we0 and the number of wait states remains the same. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT
43、 NO. 16236 DWG NO. V62/08625 REV PAGE 8 Case X Millimeters Symbol Min Max Symbol Min Max A 1.35 1.45 D/E 25.80 26.20 A1 1.60 D1/E1 23.80 24.20 A2 0.05 D2/E2 21.50 TYP b 0.17 0.27 e 0.50 BSC c 0.13 nom L 0.45 0.75 Notes: 1. All linear dimensions are in millimeters. 2. This drawing is subject to chang
44、e without notice. 3. Fall within JEDEC MO-136 FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08625 REV PAGE 9 Case outline X Terminal num
45、ber Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 3.3V_VCC31 serr_pci 61 int_aux 91 aux_data4 2 NC 32 pci_par 62 rdy_aux 92 aux_data3 3 pci_ad25 33 3.3V_VCC63 5V_VCC93 3.3V_VCC4 pci_ad24 34 1cbe_pci 64 aux_clk 94 aux_data2 5 3cbe_pc
46、i 35 GND 65 GND 95 GND 6 GND 36 pci_ad15 66 rst_aux 96 aux_data1 7 pci_idselz 37 pci_ad14 67 cs_ram 97 aux_data0 8 3.3V_VCC38 pci_ad13 68 cs_rom 98 aux_adr15 9 pci_ad23 39 pci_ad12 69 cs_aux 99 aux_adr14 10 pci_ad22 40 5V_VCC70 3.3V_VCC100 3.3V_VCC11 pci_ad21 41 pci_ad11 71 1we_aux 101 aux_adr13 12
47、5V_VCC42 3.3V_VCC72 GND 102 GND 13 pci_ad20 43 pci_ad10 73 0we_aux 103 aux_adr12 14 GND 44 pci_ad9 74 oe_aux 104 aux_adr11 15 pci_ad19 45 GND 75 3.3V_VCC105 aux_adr10 16 pci_ad18 46 NC 76 aux_data15 106 aux_adr9 17 pci_ad17 47 pci_ad8 77 aux_data14 107 3.3V_VCC18 pci_ad16 48 0cbe_pci 78 aux_data13 1
48、08 aux_adr8 19 3.3V_VCC49 3.3V_VCC79 GND 109 5V_VCC20 2cbe_pci 50 pci_ad7 80 aux_data12 110 aux_adr7 21 GND 51 GND 81 aux_data11 111 aux_adr6 22 frame_pci 52 pci_ad6 82 aux_data10 112 aux_adr5 23 irdy_pci 53 pci_ad5 83 aux_data9 113 aux_adr4 24 trdy_pci 54 pci_ad4 84 5V_VCC114 GND 25 devsel_pci 55 pci_ad3 85 aux_data8 115 aux_adr3 26 3.3V_VCC56 3.3V_VCC86 3.3V_VCC116 3.3V_VCC27 stop_pci 57 pci_ad2 87 aux_data7 117 aux_adr2 28 G
