1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil
2、/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, DUAL, 16-BIT, 1130 MSPS, TxDAC+ DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON 13-01-11 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12654 REV PAGE 1 OF 15 AMSC N/A 5962-V036-13 P
3、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual, 16-bit, 1130
4、MSPS, TxDAC+ digital to analog converter microcircuit, with an operating temperature range of -55C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifyin
5、g the item on the engineering documentation: V62/12654 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD9122-EP Dual, 16-bit, 1130 MSPS, TxDAC+ digital to analog converter 1.2.2 Case outli
6、ne(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 72 JEDEC MO-220-VNND-4 Lead Frame Chip Scale Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish design
7、ator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 3 1.3
8、Absolute maximum ratings. 1/ AVDD33 to AVSS, EPAD, CVSS, DVSS . -0.3 V to +3.6 V IOVDD to AVSS, EPAD, CVSS, DVSS -0.3 V to +3.6 V DVDD18, CVDD18 to AVSS, EPAD, CVSS, DVSS . -0.3 V to +2.1 V AVSS to EPAD, CVSS, DVSS . -0.3 V to +0.3 V EPAD to AVSS, CVSS, DVSS . -0.3 V to +0.3 V CVSS to AVSS, EPAD, DV
9、SS . -0.3 V to +0.3 V DVSS to AVSS, EPAD, CVSS . -0.3 V to +0.3 V FSADJ, REFIO, IOUT1P, IOUT1N, IOUT2P, IOUT2N to AVSS -0.3 V to AVDD33 + 0.3 V D15:0P, D15:0N, FRAMEP, FRAMEN, DCIP, DCIN to EPAD, DVSS -0.3 V to DVDD18 + 0.3 V DACCLKP, DACCLKN, REFCLKP, REFCLKN to CVSS . -0.3 V to CVDD18 + 0.3 V RESE
10、T, IRQ, CS, SCLK, SDIO, SDO to EPAD, DVSS . -0.3 V to IOVDD + 0.3 V Junction temperature . 125C Storage temperature range -65C to +150C 1.4 Thermal characteristics. Thermal resistance Case outline JAJBJCUnit Conditions Case X 20.7 10.9 1.1 C/W EPAD soldered to ground plane 2. APPLICABLE DOCUMENTS JE
11、DEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107) THE I
12、NSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1596 - IEEE Standard for low-voltage differential signals (LVDS) for scalable coherent. (Copies of these documents are available online at http:/www.ieee.org or from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscatawa
13、y, NJ 088551331. 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 1/ Stresses beyond those listed under
14、“absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions fo
15、r extended periods may affect device reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 4 3.2 Unit container. The unit container shall be marked wit
16、h the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension
17、. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function
18、shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 Timing diagram for input data port. The timing diagram for input data port shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permit
19、ted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max DC SPECIFICATIONS Resolution 16 Bits Accuracy Differential Nonline
20、arity DNL 2.1 LSB Integral Nonlinearity INL 3.7 LSB Main DAC outputs Offset error -0.001 0 +0.001 %FSR Gain error (with internal reference) -4.6 2 +4.6 Full scale output current 3/ 8.66 19.6 31.66 mA Output compliance range -1.0 +1.0 V Power Supply Rejection Ratio, AVD33 -0.3 +0.3 %FSR/V output resi
21、stance 10 M Gain ADC monotonicity 4/ Settling time to within 0.5 LSB 20 ns Main DAC temperature drift Offset 0.04 ppm/C Gain 100 Reference voltage 30 Reference Internal reference voltage 1.2 V Output resistance 5 k Analog supply voltages AVD33 3.13 3.3 3.47 V CVD18 1.71 1.8 1.89 Digital supply volta
22、ges DVDD18 1.71 1.8 1.89 V IOVDD 1.71 1.8/3.3 3.47 Power consumption 2 x Mode fDAC= 491.22 MSPS, IF = 10 MHz, PLL Off 834 mW 2 x Mode fDAC= 491.22 MSPS, IF = 10 MHz, PLL On 913 8 x Mode fDAC= 800 MSPS, IF = 10 MHz, PLL Off 1135 1259 AVDD33 55 57 mA CVDD18 85 90 DVDD18 444 505 Power down mode (Regist
23、er 0x01 = 0xF0) 6.5 18.8 mW Power up time 260 ms Operating range -55 +25 +105 C See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE
24、6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 5/ Limits Unit Min Typ Max DIGITAL SPECIFICATIONS CMOS input logic level Input VINlogic high IOVDD = 1.8 V 1.2 V IOVDD = 2.5 V 1.6 IOVDD = 3.3 V 2.0 Input VINlogic low IOVDD = 1.8 V 0.6 IOVDD = 2.5 V, 3.3 V
25、 0.8 CMOS output logic level Input VINlogic high IOVDD = 1.8 V 1.4 V IOVDD = 2.5 V 1.8 IOVDD = 3.3 V 2.4 Input VINlogic low IOVDD = 1.8 V, 2.5 V, 3.3 V 0.4 LVDS receiver inputs 6/ (Applies to data, DCI, and FRAME inputs) Input voltage range, VIAor VIB825 1675 mV Input differential threshold VIDTH-10
26、0 +100 Input differential hysteresis, VIDTHH to VIDTHL20 Receiver differential input impedance RIN80 120 LVDS input rate 7/ DAC clock input (DACCLKP, DACCLKN) Differential peak-to-peak voltage 100 500 2000 mV Common mode voltage Self-biased input, ac-coupled 1.25 V Maximum clock rate 1230 MHz REFCLK
27、 input (REFCLKP, REFCLKN) Differential peak-to-peak voltage 100 500 2000 mV Common mode voltage 1.25 V REFCLK frequency (PLL mode) 1 GHz fVCO 2.1 GHz 15.625 600 MHz REFCLK frequency (SYNC mode) See Multichip synchronization section of the manufacturer data for more conditions 0 600 Serial port inter
28、face Maximum clock rate SCLK 40 MHz Maximum pulse width high tPWH12.5 ns Minimum pulse width low tPWL12.5 Setup time, SDIO to SCLK tDS2.1 Hold time, SDIO to SCLK tDH0.75 Data valid, SDO to SCLK tDV2.85 Setup time, CSto SCLK tDCSB 1.4 See footnote at end of table. Provided by IHSNot for ResaleNo repr
29、oduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 5/ Limits Unit Min Typ Max DIGITAL INPUT DATA TIMING
30、 SPECIFICATIONS Latency (DACCLK cycles) 1 x Interpolation (With or without modulation) 64 Cycles 1 x Interpolation (With or without modulation) 135 1 x Interpolation (With or without modulation) 292 1 x Interpolation (With or without modulation) 608 Inverse Sinc 20 Fire modulation 8 Test Symbol Test
31、 conditions 2/ Limits Unit Min Typ Max AC SPECIFICATIONS Spurious-Free Dynamic Range (SFDR) fDAC= 100 MSPS, fOUT= 20 MHz 78 dBc fDAC= 200 MSPS, fOUT= 50 MHz 80 fDAC= 400 MSPS, fOUT= 70 MHz 69 fDAC= 800 MSPS, fOUT= 70 MHz 72 Two tone Intermodulation Distortion (IMD) fDAC= 200 MSPS, fOUT= 50 MHz 84 dB
32、c fDAC= 400 MSPS, fOUT= 60 MHz 86 fDAC= 400 MSPS, fOUT= 80 MHz 84 fDAC= 800 MSPS, fOUT= 100 MHz 81 Noise Spectral Density (NSD), Eight-tone, 500 kHz tone spacing fDAC= 200 MSPS, fOUT= 80 MHz -162 dBm/Hz fDAC= 400 MSPS, fOUT= 80 MHz -163 fDAC= 800 MSPS, fOUT= 80 MHz -164 W-CDMA Adjacent Channel Leaka
33、ge Ratio (ACLR), Single carrier fDAC= 491.52 MSPS, fOUT= 10 MHz 84 dBc fDAC= 491.52 MSPS, fOUT= 122.88 MHz 82 fDAC= 983.04 MSPS, fOUT= 122.88 MHz 83 W-CDMA second ACLR, single carrier fDAC= 491.52 MSPS, fOUT= 10 MHz 88 dBc fDAC= 491.52 MSPS, fOUT= 122.88 MHz 86 fDAC= 983.04 MSPS, fOUT= 122.88 MHz 88
34、 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing an
35、d other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametr
36、ic testing, product performance is assured by characterization and/or design. 2/ TMINto TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS= 20 mA, maximum sample rate, unless otherwise noted. 3/ Based on a 10 k external resistor between FSADJ and AVSS. 4/ Guaranteed. 5/ TMINto TMAX, AVDD33 =
37、3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS= 20 mA, maximum sample rate, unless otherwise noted. 6/ LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted. 7/ Maximum rate (MSPS) with DVDD and CVDD supply regulation Bus Width Interpolation factor fINTE
38、RFACE(MSPS) fDAC(MSPS) DVDD18, CVDD18 = DVDD18, CVDD18 = 1.8 V 5% 1.8 V 2% 1.9 V 2% 1.8 V 5% 1.8 V 2% 1.9 V 2% Nibble (4 Bits) 1 x 2 x 4 x 8 x 1000 1000 1000 1000 1100 1100 1100 1100 1130 1130 1130 1130 125 250 500 1000 137.5 275 550 1100 141.25 282.5 565 1130 Byte (8 Bits) 1 x 2 x 4 x 8 x 1000 1000
39、 1000 500 1100 1100 1100 550 1130 1130 1130 565 250 500 1000 1000 275 550 1100 1100 282.5 565 1130 1130 Word (16 Bits) 1 x 2 x (HB1) 2 x (HB2) 4 x 8 x 1000 800 1000 500 250 1100 900 1100 550 275 1130 900 1130 565 282.5 500 800 1000 1000 1000 550 900 1100 1100 1100 565 900 1130 1130 1130 Provided by
40、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 9 Case X D1/E1PIN 1IDENTIFIERTOP VIEW12 MAXASEATINGPLANEb48 PLSeA2A1A3BOTTOM VIEWLL1L1EXPOSEDPAD11819 3637545572PIN 1IDENT
41、IFIERD2/E2D/Ee1FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 10 Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 0
42、.80 1.00 D1/E1 9.75 BSC A1 0.80 D2/E2 5.85 6.15 A2 0.20 REF e 0.50 BSC A3 0.05 e1 8.50 REF b 0.18 0.30 L 0.30 0.50 D/E 10.00 BSC L1 0.24 0.60 NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC MO-220-VNND-4. FIGURE 1. Case outline - Continued. Case outline X Terminal number Te
43、rminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 CVDD18 19 D11P 37 D4P 55 NC 2 DACCLKP 20 D11N 38 D4N 56 AVSS 3 DACCLKN 21 D10P 39 D3P 57 AVDD33 4 CVSS 22 D10N 40 D3N 58 IOUT2P 5 FRAMEP 23 D9P 41 D2P 59 IOUT2N 6 FRAMEN 24 D9N 42 D2N 60 A
44、VDD33 7 IRQ25 D8P 43 DVDD18 61 AVSS 8 D15P 26 D8N 44 DVSS 62 REFIO 9 D15N 27 DCIP 45 D1P 63 FSADJ 10 NC 28 DCIN 46 D1N 64 AVSS 11 IOVDD 29 DVDD18 47 D0P 65 AVDD33 12 DVDD18 30 DVSS 48 D0N 66 IOUT1N 13 D14P 31 D7P 49 DVDD18 67 IOUT1P 14 D14N 32 D7N 50 SDO 68 AVDD33 15 D13P 33 D6P 51 SDIO 69 REFCLKN 1
45、6 D13N 34 D6N 52 SCLK 70 REFCLKP 17 D12P 35 D5P 53 CS71 CVDD18 18 D12N 36 D5N 54 RESET72 CVDD18 NOTES: 1. Exposed PAD (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical, thermal, and mechanical connection to the board. 2. NC = No Connect. Do not connect to this pin.
46、FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12654 REV PAGE 11 Case outline X Terminal number Mnemonic Description 1 CVDD18 1.8 V clock su
47、pply. Supplies clock receivers, clock distribution, and PLL circuitry 2 DACCLKP DAC clock input, positive. 3 DACCLKN DAC clock input, negative. 4 CVSS Clock supply common. 5 FRAMEP Frame input, Positive. This pin must be tied to DVSS if not used. 6 FRAMEN Frame input, Negative. This pin must be tied to DVDD18 if not used. 7 IRQInterrupt request. Open rain, active low output. Connect an external pull-up to IOVDD through a 10 k resistor. 8 D15P Data bit 15 (MSB), Positive. 9 D15N Data bit 15 (MSB), Negative. 10 NC No connect. Do not connect to
