1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/
2、 Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, CMOS, 8-BIT, BUFFERED MULTIPLYING DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON 13-06-17 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12659 REV PAGE 1 OF 15 AMSC N/A 5962-V10
3、3-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS, 8 bit,
4、buffered multiplying digital to analog converter microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for id
5、entifying the item on the engineering documentation: V62/12659 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD7524 CMOS, 8 bit, buffered multiplying digital to analog converter 1.2.2 Cas
6、e outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MS-012-AC Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designa
7、tor Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 3 1.3 A
8、bsolute maximum ratings. 1/ Supply voltage range (VDD) to ground (GND) -0.3 V to +17 V DAC feedback resistor (VRFEEDBACK) to GND . 25 V DAC reference voltage input (VREF) to GND . 25 V Digital input voltage to GND . -0.3 V to VDD+ 0.3 V DAC current output (OUT1), DAC analog ground (OUT2) to GND -0.3
9、 V to VDD+ 0.3 V Power dissipation (PD) : To 75C 450 mW Derates above 75C by 6 mW/C Storage temperature range (TSTG) -65C to +150C Lead temperature (soldering, 10 seconds) . 300C 1.4 Recommended operating conditions. 2/ Operating free-air temperature range (TA) -55C to +125C 1.5 Thermal characterist
10、ics. Thermal resistance, junction to case (JC) . 43C/W (Non-standard 4 layer board) Thermal resistance, junction to ambient (JA) 81C/W (Non-standard 4 layer board) 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only,
11、 and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Use of this product beyond the manufacturers d
12、esign rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME C
13、OLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wil
14、son Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identif
15、ication (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1
16、.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections s
17、hall be as shown in figure 2. 3.5.3 Timing waveforms. The timing waveforms shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 5 TA
18、BLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VREF= 10 V, VOUT1= VOUT2= 0 V, unless otherwise specifiedTemperature, TADevice type Limits Unit Min Max Static performance. Resolution VDD= 5 V and 15 V 25C 01 8 Bits -55C to +125C 8 Relative accuracy VDD= 5 V and 15 V 25C 01 1
19、/2 LSB -55C to +125C 1/2 Monotonicity 01 Guaranteed Gain error 2/ AE VDD= 5 V 25C 01 2 1/2 LSB VDD= 15 V 1 1/4 VDD= 5 V -55C to +125C 3 1/2 VDD= 15 V 1 1/2 Average gain 3/ temperature coefficient VDD= 5 V 25C 01 40 ppm/ C (Measured from 25C to -55C or from 25C to +125C) VDD= 15 V 10 VDD= 5 V -55C to
20、 +125C 40 VDD= 15 V 10 DC supply rejection 3/ Gain/ VDD= 5 V, VDD= 10% 25C 01 0.08 %FSR/ VDD0.002 typical %max VDD= 15 V, VDD= 10% 0.02 0.001 typical VDD= 5 V, VDD= 10% -55C to +125C 0.16 0.01 typical VDD= 15 V, VDD= 10% 0.04 0.005 typical See footnotes at end of table. Provided by IHSNot for Resale
21、No reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VREF= 10 V, VOUT1= VOUT2= 0 V, unless otherwise spec
22、ifiedTemperature, TADevice type Limits Unit Min Max Static performance continued. Output leakage current, pin 1 IOUT1DB0 to DB7 = 0 V, VDD= 5 V 25C 01 50 nA WR , CS = 0 V, VDD= 15 V 50 VREF= 10 V VDD= 5 V -55C to +125C 400 VDD= 15 V 200 Output leakage current, pin 2 IOUT2DB0 to DB7 = VDD, VDD= 5 V 2
23、5C 01 50 nA WR , CS = 0 V, VDD= 15 V 50 VREF= 10 V VDD= 5 V -55C to +125C 400 VDD= 15 V 200 Dynamic performance. Output current 3/ settling time (to 1/2 LSB) OUT1 load = 100 , VDD= 5 V 25C 01 400 ns CEXT= 13 pF, VDD= 15 V 250 WR , CS = 0 V, VDD= 5 V -55C to +125C 500 DB0 to DB7 = 0 V to VDDto 0 V, V
24、DD= 15 V 350 AC feedthrough at 3/ at OUT1 VREF= 10 V, VDD= 5 V 25C 01 0.25 %FSR 100 kHz sine wave, VDD= 15 V 0.25 DB0 to DB7 = 0 V, VDD= 5 V -55C to +125C 0.5 WR , CS = 0 V, VDD= 15 V 0.5 AC feedthrough at 3/ at OUT2 VREF= 10 V, VDD= 5 V 25C 01 0.25 %FSR 100 kHz sine wave, VDD= 15 V 0.25 DB0 to DB7
25、= 0 V, VDD= 5 V -55C to +125C 0.5 WR , CS = 0 V, VDD= 15 V 0.5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 7 TABLE I. Elect
26、rical performance characteristics Continued. 1/ Test Symbol Conditions VREF= 10 V, VOUT1= VOUT2= 0 V, unless otherwise specifiedTemperature, TA Device type Limits Unit Min Max Reference input. Reference input 4/ RINVDD= 5 V and 15 V 25C 01 5 20 k (VREFpin to GND) -55C to +125C 5 20 Analog outputs. O
27、utput capacitance 3/ COUT1 VDD= 5 V and 15 V, 25C 01 120 pF (pin 1) DB0 to DB7 = VDD, -55C to +125C 120 COUT2 WR , CS = 0 V, 25C 30 (pin 2) -55C to +125C 30 COUT1 VDD= 5 V and 15 V, 25C 30 (pin 1) DB0 to DB7 = 0 V, -55C to +125C 30 COUT2 WR , CS = 0 V, 25C 120 (pin 2) -55C to +125C 120 Digital input
28、s. Input high voltage requirement VIHVDD= 5 V 25C 01 2.4 V VDD= 15 V 13.5 VDD= 5 V -55C to +125C 2.4 VDD= 15 V 13.5 Input low voltage requirement VILVDD= 5 V 25C 01 0.8 V VDD= 15 V 1.5 VDD= 5 V -55C to +125C 0.5 VDD= 15 V 1.5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproductio
29、n or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VREF= 10 V, VOUT1= VOUT2= 0 V, unless otherwise specifiedTemperatu
30、re, TA Device type Limits Unit Min Max Digital inputs - continued. Input current IINVDD= 5 V, VIN= 0 V or VDD25C 01 1 A VDD= 15 V, VIN= 0 V or VDD1 VDD= 5 V, VIN= 0 V or VDD-55C to +125C 10 VDD= 15 V, VIN= 0 V or VDD10 Input capacitance 3/ CINVDD= 5 V and 15 V, VIN= 0 V, 25C 01 5 pF DB0 to DB7 -55C
31、to +125C 5 VDD= 5 V and 15 V, VIN= 0 V, 25C 20 WR , CS -55C to +125C 20 Switching characteristics. See figure 3. Chip select to write 5/ setup time tCStWR= tCSVDD= 5 V 25C 01 170 ns VDD= 15 V 100 VDD= 5 V -55C to +125C 240 VDD= 15 V 150 Chip select to write hold time tCHVDD= 5 V and 15 V 25C 01 0 ns
32、 -55C to +125C 0 Write pulse width tWRtCS tWR, VDD= 5 V 25C 01 170 ns tCH 0 VDD= 15 V 100 VDD= 5 V -55C to +125C 240 VDD= 15 V 150 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZ
33、E A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 9 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions VREF= 10 V, VOUT1= VOUT2= 0 V, unless otherwise specifiedTemperature, TA Device type Limits Unit Min Max Switching characteristics - continued. See figure 3 Data
34、 setup time tDSVDD= 5 V 25C 01 135 ns VDD= 15 V 60 VDD= 5 V -55C to +125C 170 VDD= 15 V 100 Data hold time tDHVDD= 5 V and 15 V 25C 01 10 ns -55C to +125C 10 Power supply Power supply current IDDAll digital inputs VDD= 5 V 25C 01 1 mA VILor VIHVDD= 15 V 2 VDD= 5 V -55C to +125C 2 VDD= 15 V 2 All dig
35、ital inputs VDD= 5 V 25C 100 A 0 V or VDDVDD= 15 V 100 VDD= 5 V -55C to +125C 500 VDD= 15 V 500 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the
36、 full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Gain error is measured using internal feedback resistor. Full scale range (FSR) = VREF. 3/ Guaranteed not test
37、ed. 4/ DAC thin film resistor temperature coefficient is approximately 300 ppm/C. 5/ AC parameter, sample tested at 25C to ensure conformance to specification. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE
38、A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 10 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 11 Case X Symbol Dimension
39、s Inches Millimeters Min Max Min Max A 0.0531 0.0689 1.35 1.75 A1 0.0039 0.0098 0.10 0.25 b 0.0122 0.0201 0.31 0.51 c 0.0067 0.0098 0.17 0.25 D 0.3858 0.3937 9.80 10.00 E 0.1496 0.1575 3.80 4.00 E1 0.2283 0.2441 5.80 6.20 e 0.0500 BSC 1.27 BSC L 0.0157 0.0500 0.40 1.27 NOTES: 1. Controlling dimensio
40、ns are millimeter, inch dimensions are given for reference only. 2. Falls within reference to JEDEC MS-012-AC. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT
41、NO. 16236 DWG NO. V62/12659 REV PAGE 12 Device type 01 Case outline X Terminal number Terminal symbol 1 OUT1 2 OUT2 3 GND 4 DB7 (MSB) 5 DB6 6 DB5 7 DB4 8 DB3 9 DB2 10 DB1 11 DB0 (LSB) 12 CS 13 WR 14 VDD15 VREF16 RFEEDBACKFIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or
42、 networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 13 Terminal symbol Description OUT1 DAC current output. OUT2 DAC analog ground. This pin should normally be tied to the analog ground of the system. GND Grou
43、nd. DB7 (MSB) to DB0 (LSB) Parallel data bit 7 to data bit 0. CS Chip select input. Active low. Used in conjunction with WR to load parallel data to the input latch. WR Write. When low, use in conjunction with CS to load parallel data. VDDPositive power supply input. These parts can be operated with
44、 a supply of 5 V. VREFDAC reference voltage input terminal. RFEEDBACKDAC feedback resistor pin. Establish voltage output of the DAC by connecting to external amplifier output. FIGURE 2. Terminal connections - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic
45、ense from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 14 NOTES: 1. All input signal rise and fall times measured from 10% to 90% of VDD. VDD= 5 V, tR= tF= 20 ns; VDD= 15 V, tR= tF= 40 ns. 2. Timing measurement reference level is (VIH+ VIL) / 2.
46、 3. tDS+ tDHis approximately constant at 145 ns minimum at 25C, VDD= 5 V and tWR= 170 ns minimum. The device is specified for a minimum tDHof 10 ns. However, in applications where tDH 10 ns, tDSmay be reduced accordingly up to the limit tDS= 65 ns, tDH= 80 ns. FIGURE 3. Timing waveforms. Provided by
47、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12659 REV PAGE 15 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requ
