1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Vendor requested correction to Table IA; parameter (Write disable time - tWHWL) from 1 ns to 2 ns minimum. ksr 10-07-07 Charles F. Saffle B Added device types 05 and 06. Modified paragraphs 1.3, 1.4, and 1.5; also added new footnote for paragraph
2、 1.5 and renumbered existing footnotes. Modified Table IA to incorporate device types 05 and 06. Editorial changes to boilerplate paragraphs. ksr 11-03-07 Charles F. Saffle C Removed footnote from 1.2.2 and re-sequenced footnotes in sections 1.3 through 1.5. Updated RHA parametric limit of SEL and S
3、EU in 1.5 and table IB. Changed minimum limit of tAVCL from 200ns to 400ns and added tCHAV and tCLAX to Table IA. Revised EDAC Control register cycle timing waveform and related notes in Figure 5. Updated boilerplate for current requirements and removed all references to class M. lht 13-05-13 Charle
4、s F. Saffle REV SHEET REV C C C C C C C C C C C C C C SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritim
5、e.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Cheri Rida THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Robert M. Heber MICROCIRCUIT, MEMORY, DIGITAL, CMOS, RADIATION-HARDENED, 512K X 32-BIT (16MB) WITH EMBEDDED EDAC, LOW VOLTAGE SRAM, MONOLITHIC SILICON AND AGENCIES OF THE DE
6、PARTMENT OF DEFENSE DRAWING APPROVAL DATE 09-02-23 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-06261 SHEET 1 OF 28 DSCC FORM 2233 APR 97 5962-E350-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-
7、06261 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lea
8、d finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R 06261 01 Q X C Federal RHA Device Device Case Lead st
9、ock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA desi
10、gnator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 UT8ER512K32M 512K X 32-bit CMOS SRAM (MIL-TEMP) master 20 ns 02 UT8ER512K32M 512K X 32-bit CMOS SRAM (EXTENDE
11、D-TEMP) master 20 ns 03 UT8ER512K32S 512K X 32-bit CMOS SRAM (MIL-TEMP) slave 20 ns 04 UT8ER512K32S 512K X 32-bit CMOS SRAM (EXTENDED-TEMP) slave 20 ns 05 UT8ER512K32M 512K X 32-bit CMOS SRAM (MIL-TEMP) master 20 ns 06 UT8ER512K32S 512K X 32-bit CMOS SRAM (MIL-TEMP) slave 20 ns 1.2.3 Device class de
12、signator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 an
13、d as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 68 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST
14、ANDARD MICROCIRCUIT DRAWING SIZE A 5962-06261 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range, (VDD1) . -0.3 V dc to +2.1 V dc Supply voltage range, (VDD2) . -0.3 V dc to +3.8 V dc Voltage range o
15、n any pin . -0.3 V dc to +3.8 V dc Input current, dc . 10 mA Power dissipation 5 W Operating case temperature range, (TC) Devices 01, 03, 05, 06 -55C to +125C Devices 02, 04 -40C to +125C Storage temperature range, (TSTG) -65C to +150C Junction temperature, (TJ) . +150C Thermal resistance, junction-
16、to-case, (JC): Case X . +5C/W 1.4 Recommended operating conditions. Supply voltage range, (VDD1) . +1.7 V dc to +1.9 V dc 3/ Supply voltage range, (VDD2) . +3.0 V dc to +3.6 V dc Supply voltage, (VSS) . 0 V dc Input voltage, dc 0 V dc to VDD2 Operating case temperature range, (TC) Devices 01, 03, 05
17、, 06 -55C to +125C Devices 02, 04 -40C to +125C 1.5 Radiation features Maximum total dose available: For device types 01-04 (dose rate =50 - 300 rads(Si)/s): 100 krads(Si) 4/ For device types 05-06 (effective dose rate = 1 rad(Si)/s) . 100 krads(Si) 5/ Single event phenomenon (SEP): No SEL at effect
18、ive LET (see 4.4.4.3 and table IB ) 111 MeV-cm2/mg 6/ 7/ No SEU occurs at onset LET (see 4.4.4.3 and table IB ) (Adams 90% worst case environment SER = 8.1 x 10-16 errors/bit-day) . 0.8 MeV-cm2/mg 7/ 8/ Neutron irradiation 3.0 x 1014 n/cm2 1/ Stresses above the absolute maximum rating may cause perm
19、anent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltage values in this drawing are with respect to VSS. 3/ For increased noise immunity, supply voltage (VDD1) can be increased to 2.0 V. The parameters in Table IA, (Electrica
20、l performance characteristics) are guaranteed through characterization at VDD1 = 2.0 V dc. Unless otherwise specified. 4/ For device types 01 - 04 are irradiated at a dose rate = 50-300 rads (Si)/s in accordance with MIL-STD-883, method 1019, condition A, and radiation end point limits for the noted
21、 parameters are guaranteed to a maximum total dose specified herein. 5/ For device types 05 - 06 are irradiated at a dose rate = 50-300 rads (Si)/s in accordance with MIL-STD-883, method 1019, condition A, and radiation end point limits for the noted parameters are guaranteed to a maximum total dose
22、 specified herein. The effective dose rate after extended room temperature anneal = 1 rad (Si)/s per MIL-STD-883, method 1019, condition A section 3.11.2. The total dose specification for these devices only applies to a low dose rate environment. 6/ Contact the device manufacturer for detailed lot i
23、nformation. 7/ Limits are guaranteed by design or process, but not production tested unless specified by customer in purchase order or contract. 8/ Assuming geosynchronous orbit, Adams 90% worst environment and 152 KHz default scrub rate (97.0% SRAM availability) in terrestrial environment. Provided
24、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06261 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, an
25、d handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Cir
26、cuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780
27、 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of t
28、his document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ASTM INTERNATIONAL (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irra
29、diation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Copies of this document are
30、available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201). (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents als
31、o may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws
32、and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. Th
33、e modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. Provided by IHSNot for Res
34、aleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06261 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and Fig
35、ure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on Figure 2. 3.2.3 Truth table. The truth table shall be as specified on Figure 3. 3.2.4 Output load circuit. The output load circuit for functional tests shall be as specified on Figure 4. 3.2.5 Tester timing characte
36、ristics and timing waveforms. The tester AC timing characteristics and timing waveforms shall be as specified on Figure 5 and applies to capacitance, read cycle, and write cycle measurements unless otherwise specified. 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintai
37、ned by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.2.7 Functional tests. Various functional tests used to test this device are contained in the appendix (herein). If the test patterns cannot be implemented
38、 due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity up
39、on request. For device classes Q and V, alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteri
40、stics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical
41、 test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire S
42、MD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certifica
43、tion/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requir
44、ements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein
45、. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDAR
46、D MICROCIRCUIT DRAWING SIZE A 5962-06261 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C (devices01,03, 05, 06) -40C TC +125C (devices02,04) +1.7 V VDD1 +1.9
47、V +3.0 V VDD2 +3.6 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max High-level input voltage VIH 1,2,3 All .7*VDD2 V Low-level input voltage VIL 1,2,3 All .3*VDD2 V High-level output voltage VOH IOH = -4mA, VDD2 = VDD2 (min) 1,2,3 All .8*VDD2 V Low-level output voltage
48、2/ VOL IOL = 8 mA, VDD2 = VDD2 (min) 1,2,3 All .2*VDD2 V Input capacitance 3/ CIN f = 1 MHz 0 V see 4.4.1e 4 All 12 pF Bidirectional I/O capacitance 3/ CIO 4 All 12 pF Input leakage current IIN VlN = VDD2 and VSS 1,2,3 All -2 2 A Three state output leakage current 4/ IOZ VO = VDD2 and VSS, VDD2 = VDD2 (max); G =VDD2 (max) 1,2,3 All -2 2 A Short-circuit output current 5/ 6/ IOS VDD2 = VDD2 (max), VO = VDD2 VDD2 = VDD2 (max), VO = VSS 1,2,3 All -100 100 mA Supply current operating
