1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change output current, Io. Complete document update. 85-03-06 N. A. Hauck B Case E inactive for new design. Remove Vendor FSCM 04713. Editorial changes throughout. 85-07-25 N. A. Hauck C Changes in accordance with NOR 5962-R081-92 92-07-07 Phu Ng
2、uyen D Redraw with changes. Update current requirements. Editorial changes throughout. - gap 05-10-26 Raymond Monnin CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Greg A. Pitz DEFENSE SUPPLY CENTER COLUMBUS
3、 STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY N. A. Hauck MICROCIRCUITS, DIGITAL, ADVANCED LOW-POWER SCHOTTKY TTL, J-K FLIP-FLOPS, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRA
4、WING APPROVAL DATE 84-04-12 MONOLITHIC SILICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 14933 84000 SHEET 1 OF 11 DSCC FORM 2233 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-APR 97 5962-E021-06 Provided by IHSNot for ResaleNo reproduction or net
5、working permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84000 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class le
6、vel B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84000 01 E X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) id
7、entify the circuit function as follows: Device type Generic number Circuit function 01 54ALS109 Dual J-K flip-flop with clear and preset (active high) 02 54ALS112A Dual J-K flip-flop with clear and preset (active low) 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and a
8、s follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 dual-in-line F GDFP2-F16 or CDFP3-F16 16 flat package 2 CQCC1-N20 20 square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings.
9、 Supply voltage range . -0.5 V dc to +7.0 V dc Input voltage range -0.5 V dc to VCC+0.5 V dc DC VCCor GND current (per pin) 50 mA Storage temperature range -65C to +150C Maximum power dissipation (PD) per flip-flop 1/: Device type 01 . 11 mW Device type 02 . 13 mW Lead temperature (soldering, 10 sec
10、onds) . +300C Thermal resistance, junction-to-case (JC): See MIL-STD-1835 Junction temperature (TJ) . +175C _ 1/ Must withstand the added PDdue to short circuit test (e.g., IO). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DR
11、AWING SIZE A 84000 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage (VCC) . 4.5 V dc to +6.0 V dc Minimum high level input voltage (VIH) . 2.0 V Maximum low level input voltage (VIL) . 0.8 V C
12、ase operating temperature range (TC) . -55C to +125C Minimum width of CLOCK pulse (tp CLOCK): Device type 01 16.5 ns Device type 02 20 ns Minimum width of CLEAR pulse (tp CLEAR ): Device types 01 and 02 15 ns Minimum width of PRESET pulse (tp PRESET ): Device types 01 and 02 15 ns Minimum data setup
13、 time: Device type 01 15 ns Device type 02 25 ns Minimum CLR or PRE inactive state setup time: Device type 01 10 ns Device type 02 22 ns Minimum data hold time (tp HOLD): Device types 01 and 02 0 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specifi
14、cation, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Spec
15、ification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings.
16、 (Copies of these documents are available online at http:/assist.daps.dla.mil;quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of th
17、is drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro
18、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84000 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class
19、 level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance wit
20、h the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. T
21、hese modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be
22、as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Logic diagrams. The logic diagrams shall be as specified on figure
23、2. 3.2.4 Truth tables. The truth tables shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electri
24、cal test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herei
25、n. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in
26、accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted
27、 to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be pro
28、vided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufac
29、turers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84000 DEFENSE SUPPLY CEN
30、TER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC+125C unless otherwise specified Device type Group A subgroups Min Max Unit High-level output voltage VOHVCC= 4.5 V, VIH= 2.0 V,
31、 IOH= -400 A, VIL= 0.8 V All 1, 2, 3 2.5 V Low-level output voltage VOLVCC= 4.5 V, VIH= 2.0 V, IOH= 4 mA, VIL= 0.8 V All 1, 2, 3 0.4 V Input clamp voltage VICVCC= 4.5 V, IIN= -18 mA, TC= 25C All 1 -1.5 V Low level input current at J or K IIL1VCC= 5.5 V, VIN= 0.4 V All 1, 2, 3 -200 A Low level input
32、current PRE , CLR , or CLK IIL2VCC= 5.5 V, VIN= 0.4 V All 1, 2, 3 -400 A High level input current at J or K IIH1VCC= 5.5 V, VIN= 2.7 V All 1, 2, 3 20 A High-level input current at PRE or CLR IIH2VCC= 5.5 V, VIN= 2.7 V All 1, 2, 3 40 A High level input current at CLK IIH3VCC= 5.5 V, VIN= 2.7 V All 1,
33、 2, 3 80 A Output current 1/ IOVCC= 5.5 V, VO= 2.25 V All 1, 2, 3 -20 -112 mA 01 1, 2, 3 4 Supply current 2/ ICCVCC= 5.5 V, VIN= 0 V 02 4.5 mA High level input current J or K IH4VCC= 5.5 V, VIN= 7.0 V All 1, 2, 3 100 A High level input current PRE or CLR IIH5VCC= 5.5 V, VIN= 7.0 V All 1, 2, 3 200 A
34、High level input current at CLK IIH6VCC= 5.5 V, VIN= 7.0 V All 1, 2, 3 400 A 01 9, 10, 11 3 18 tPLH102 3 26 ns 01 9, 10, 11 5 17 Propagation delay time CLR or PRE to output tPHL102 4 23 ns 01 9, 10, 11 5 21 ns tPLH202 3 23 01 9, 10, 11 5 20 Propagation delay time CLK to output tPHL202 5 24 01 9, 10,
35、 11 30 Maximum clock frequency fmaxVCC= 5.0 V, CL= 50 pF +10%, RL= 500 02 25 MHz 1/ The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, IOS. 2/ ICCis measured with outputs open with J, K, CLK and PRE grounded; then
36、with J, K, CLK, and CLR grounded. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84000 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 FIGURE 1. Terminal co
37、nnections (top view). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84000 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 FIGURE 1. Terminal connections (t
38、op view). - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84000 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 FIGURE 2. Logic diagrams. Provid
39、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84000 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Device type 01 INPUTS OUTPUTS PRESET CLEAR CLOCK J K Q Q L H
40、X X X H L H L X X X L H L L X X X H* H* H H L L L H H H H L TOGGLE H H L H QOQOH H H H H L H H L X X QOQOH = High level (steady state) L = Low level (steady state) X = Irrelevant = Transition from low to high level QO= The level of Q before the indicated steay state input conditions were established
41、. TOGGLE: Each output changes to the complement of its previous level on each clock transition. * This configuration is nonstable; that is it will not persist when preset and clear inputs return to their inactive (high) level. Device type 02 INPUTS OUTPUTS PRESET CLEAR CLOCK J K Q Q L H X X X H L H
42、L X X X L H L L X X X H* H* H H L L QOQOH H L H L H H H L H L H H H H H TOGGLE H H H X X QOQOH = High level (steady state) L = Low level (steady state) X = Irrelevant = Transition from high to low level QO= The level of Q before the indicated steay state input conditions were established. TOGGLE: Ea
43、ch output changes to the complement of its previous level on each clock transition. * This configuration is nonstable; that is it will not persist when preset and clear inputs return to their inactive (high) level. FIGURE 3. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking pe
44、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84000 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF
45、-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C o
46、r D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with th
47、e intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test
48、 requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) - - - Final electrical test parameters (method 5004) 1*,2, 3, 9, 10, 11 Group A test requirements (method 5005) 1, 2, 3, 7, 9, 10, 11 Groups C and D end-point electrical parameters (method 5005) 1, 2, 3 * PDA applies to subgroup 1. 4.3 Quality conformance inspection. Quality conformance
