1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED D Update boilerplate to MIL-PRF-38535 requirements. - jak 01-09-05 Thomas M. Hess E Made change to paragraph 3.5. Update boilerplate to MIL-PRF-38535 requirements. - LTG 05-01-14 Thomas M. Hess F Correct the expression of IOfor VOHand VOLin table I
2、. Update boilerplate - jak 11-7-21 Thomas M. Hess Current CAGE CODE is 67268 REV SHEET REV SHEET REV STATUS REV F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 https:/www.landandmaritime.dla.mil/ STANDARD
3、 MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Nelson A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, HEX BUFFER WITH THREE-STATE OUTPUTS, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 85-05-28 MONOLITHIC SILICON AMS
4、C N/A REVISION LEVEL F SIZE A CAGE CODE 14933 85002 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E376-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 85002 REVISION L
5、EVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example
6、: 85002 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 54HC367 Hex buffer with three-state outputs 1.2.2 Case outlines. The case
7、outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MI
8、L-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range -0.5 V dc to VCC+0.5 V dc DC output voltage range -0.5 V dc to VCC+0.5 V dc DC input diode current . 20 mA DC output diode current . 20 mA DC output current (per pin) 35
9、 mA DC VCCor ground current (per pin) 70 mA Maximum power dissipation (PD) 500 mW 2/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) . +175C Storage temperature range (TSTG) . -65C to +150C 1.4 Recommended operatin
10、g conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) . -55C to +125C Input rise or fall time: VCC= 2.0 V 0 to 1000 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns 1/ Unless otherwise specified, all voltages are referenced to ground. 2/ For TC= +100C
11、to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 85002 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.
12、1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPE
13、CIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Sta
14、ndard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government pu
15、blications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD 7-A - Standard for Description of 54/74H
16、CXXXX and 54/74HCTXXXX High-Speed CMOS Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 2.3 Order of precedence. In the event of a conflict between the text of th
17、is drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in acco
18、rdance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-
19、38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications s
20、hall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The
21、design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The
22、 truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SI
23、ZE A 85002 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics
24、are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be
25、in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN d
26、evices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required f
27、rom a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 and QML-38535 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the require
28、ments of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA
29、Land and Maritime-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore do
30、cumentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 85002 REVISION LEVEL F SHEET 5 DSCC FORM 2
31、234 APR 97 Table I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max High-level output voltage VOHVIN= VIHor VILIOH= 20 A VCC= 2.0 V 1, 2, 3 1.9 V VCC= 4.5 V 1, 2, 3 4.4 VCC= 6.0 V 1, 2, 3 5.9 VIN= V
32、IHor VILIOH= -6.0 mA VCC= 4.5 V 1, 2, 3 3.7 VIN= VIHor VILIOH= -7.8 mA VCC= 6.0 V 1, 2, 3 5.2 Low-level output voltage VOLVIN= VIHor VILIOL= 20 A VCC= 2.0 V 1, 2, 3 0.1 V VCC= 4.5 V 1, 2, 3 0.1 VCC= 6.0 V 1, 2, 3 0.1 VIN= VIHor VILIOL= 6.0 mA VCC= 4.5 V 1, 2, 3 0.4 VIN= VIHor VILIOL= +7.8 mA VCC= 6.
33、0 V 1, 2, 3 0.4 High-level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low-level input voltage VIL2/ VCC= 2.0 V 1, 2, 3 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Quiescent current ICCVIN= VCCor GND VCC= 6.0 V 1, 2
34、, 3 160 A Input leakage current IINVIN= VCCor GND VCC= 6.0 V 1, 2, 3 1.0 A Three-state output leakage current IOZVIN= VCCor GND VCC= 6.0 V 1, 2, 3 10.0 A Functional tests See 4.3.1d 7 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license
35、from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 85002 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 Table I. Electrical performance characteristics - Continued. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroup
36、s Limits Unit Min Max Propagation delay, time, An to Yn tPLH, tPHL4/ CL= 50 pF See figure 4 VCC= 2.0 V 9 120 ns 10, 11 180 VCC= 4.5 V 9 24 10, 11 36 VCC= 6.0 V 9 20 10, 11 38 Propagation delay, time, output enable, OEnnullnullnullnullnullnullto Yn tPZH, tPZL4/ CL= 50 pF See figure 4 VCC= 2.0 V 9 190
37、 ns 10, 11 285 VCC= 4.5 V 9 38 10, 11 57 VCC= 6.0 V 9 35 10, 11 52 Propagation delay, time, output disable OEnnullnullnullnullnullnullto Yn tPHZ, tPLZ4/ CL= 50 pF See figure 4 VCC= 2.0 V 9 175 ns 10, 11 265 VCC= 4.5 V 9 35 10, 11 53 VCC= 6.0 V 9 31 10, 11 46 Transition time, output rise and fall tim
38、es tTHL, tTLH4/ CL= 50 pF See figure 4 VCC= 2.0 V 9 60 ns 10, 11 90 VCC= 4.5 V 9 12 10, 11 18 VCC= 6.0 V 9 10 10, 11 15 1/ For a power supply of 5.0 V 10% the worst case output voltage (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designed with this supply. Worst cas
39、e VINand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at VCC= 5.5 V is 3.85 V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 150 pF, determines the no load d
40、ynamic power consumption, PD= CPD VCC2 f+ICC VCC; and the no load dynamic current consumption, IS= CPDVCCf+ICC. 2/ VIHand VILtests not required if applied as forcing functions for VOHor VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the limits specified in tab
41、le I. 4/ Transition times (tTLH, tTHL) shall be guaranteed, if not tested, to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 85002
42、REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines E and F 2 Terminal number Terminal symbol 1 OE1nullnullnullnullnullnullNC 2 A1 OE1nullnullnullnullnullnull3 Y1 A1 4 A2 Y1 5 Y2 A2 6 A3 NC 7 Y3 Y2 8 GND A3 9 Y4 Y3 10 A4 GND 11 Y5 NC 12 A5 Y4 13 Y6 A4 14 A6 Y5 15 OE2nullnulln
43、ullnullnullnullA5 16 VCCNC 17 - - - Y6 18 - - - A6 19 - - - OE2nullnullnullnullnullnull20 - - - VCCNC = No connection Pin Description Symbol Description An (n = 1 to 6) Data inputs Yn (n = 1 to 6) Data outputs OEnnullnullnullnullnullnull(n = 1 or 2) Output enables (active low) FIGURE 1. Terminal con
44、nections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 85002 REVISION LEVEL F SHEET 8 DSCC FORM 2234 APR 97 Inputs Outputs OEnnullnullnullnullnullnullAn Yn H X Z
45、X X Z L H H L L L H = High voltage level L = Low voltage level X = Irrelevant Z = High impedance FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUM
46、BUS, OHIO 43218-3990 SIZE A 85002 REVISION LEVEL F SHEET 9 DSCC FORM 2234 APR 97 PARAMETER RLCLS1 S2 tPZH1k 50 pF Open Closed tPZLClosed OpentPHZ1k 50 pF Open Closed tPLZClosed OpentPLH,tPHL or tTHL,tTLH- 50 pF Open Open NOTES: 1. CL= 50 pF minimum or equivalent (includes test jig and probe capacita
47、nce). 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. RL= 1 k or equivalent. 4. Input signa
48、l from pulse generator: VIN= 0.0 V to VCC; PRR 1MHz; ZO= 50; tr = 6.0 ns; tf= 6.0 ns; trand tfshall be measured from 0.1 VCCto 0.9 VCC and from 0.9 VCC to 0.1 VCC, respectively; duty cycle = 50 percent. 5. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 6. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC
