1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Table I, page 7; correct SCLR minimum limit. Change code ident. no. to 67268. Page 4, VOHand VOL, Editorial corrections for VIN. Page 11, Fig. 3; Correct CCO output. Editorial Changes. 87-10-15 R. P. Evans B Table I, change Min. Limits on tS1, tS
2、5, and tS6. Editorial changes throughout. -les 00-02-28 Raymond Monnin C Update to current requirements. Editorial changes throughout. gap 06-03-08 Raymond Monnin D Update drawing to current MIL-PRF-38535 requirement. -jt 13-07-24 C. SAFFLE CURRENT CAGE CODE 67268 The original first page of this dra
3、wing has been replaced. REV SHEET REV D D SHEET 15 16 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Monica Grosel DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DR
4、AWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY D. A. DiCenzo APPROVED BY N. A. Hauck MICROCIRCUIT, DIGITAL, BIPOLAR SYNCHRONOUS FOUR-BIT BINARY UP-DOWN COUNTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 87-04-01 AMSC N/A REVISION LEVEL D SIZE A CAGE
5、 CODE 14933 5962-87544 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E376-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM
6、 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87544 01 R A Draw
7、ing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 25LS2569 Synchronous four-bit binary up-down counter with three state outputs 1.2.2 Case o
8、utlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is
9、as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage . -0.5 V dc to +7.0 V dc Input voltage -1.5 V dc to +5.5 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) 1/ . 0.7W Lead temperature (soldering, 10 seconds) +300C Thermal resistance, ju
10、nction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +150C DC input current -30 mA to +5.0 mA DC output current into output . 30 mA 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC) . -55C to +125C Minimum high-lev
11、el input voltage (VIH) +2.0 V dc Maximum low-level input voltage (VIL) . +0.7 V dc Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET
12、3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the s
13、olicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTME
14、NT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, P
15、A 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.
16、 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified m
17、anufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Mana
18、gement (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify
19、when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connec
20、tions. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagrams. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuits. The switching waveforms and test circuits s
21、hall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or netw
22、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V Group A su
23、bgroups Limits Unit unless otherwise specified Min Max High level output voltage VOHVCC= +4.5 V, VIN= 0.7 V or 2.0 V Y outputs IOH= -1.0 mA 1, 2, 3 2.4 V IOH= -440 A CCO, RCO outputs 1, 2, 3 2.5 V Low level output voltage VOLVCC= +4.5 V, VIN= 0.7 V or 2.0 V IOL= 4.0 mA 1, 2, 3 0.4 V IOL= 8.0 mA 1, 2
24、, 3 0.45 V Input clamp voltage VICIIN= -18 mA, VCC= 4.5 V 1, 2, 3 -1.5 V High level input current IIH1VCC= +5.5 V, VIN= 2.7 V 1, 2, 3 20 A IIH2VCC= +5.5 V, VIN= 7.0 V 1, 2, 3 100 A Low level input current IILVCC= +5.5 V, VIN= 0.4 V ACLR , OE , U/ D , LOAD 1, 2, 3 -300 A A, B, C, D, CP, CEP 1, 2, 3 -
25、400 A CET , SCLR 1, 2, 3 -650 A Low level input current IOZVCC= +5.5 V VOUT= 0.4 V 1, 2, 3 -20 A VOUT= 2.4 V 1, 2, 3 20 A Output short circuit current IOSVCC= +5.5 V, 1/ VOUT= 0.0 V 1, 2, 3 -15 -85 mA Power supply current ICCVCC= +5.5 V, OE = High All inputs = GND 1, 2, 3 43 mA See footnotes at end
26、of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics -
27、 Continued. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Limits Unit unless otherwise specified Min Max Functional testing See 4.3.1c 7, 8 Propagation delay time clock to any Q LOAD = low tPLH1 RL1= 5 k RL2= 2 k (figure 4) CL= 50 pF 2/ 9, 10, 11 24 ns CL= 15 pF 3/ 9 18 tPHL1
28、 CL= 50 pF 2/ 9, 10, 11 35 ns CL= 15 pF 3/ 9 21 Propagation delay time clock to any Q LOAD = high tPLH2 CL= 50 pF 2/ 9, 10, 11 24 ns CL= 15 pF 3/ 9 18 tPHL2 CL= 50 pF 2/ 9, 10, 11 35 ns CL= 15 pF 3/ 9 21 Propagation delay time CET to RCO tPLH3 RL= 2 k (figure 4) CL= 50 pF 2/ 9, 10, 11 19 ns CL= 15 p
29、F 3/ 9 16 tPHL3 CL= 50 pF 2/ 9, 10, 11 21 ns CL= 15 pF 3/ 9 14 Propagation delay time U/ D to RCO tPLH4 CL= 50 pF 2/ 9, 10, 11 28 ns CL= 15 pF 3/ 9 23 tPHL4 CL= 50 pF 2/ 9, 10, 11 30 ns CL= 15 pF 3/ 9 20 Propagation delay time clock to RCO tPLH5 CL= 50 pF 2/ 9, 10, 11 40 ns CL= 15 pF 3/ 9 35 tPHL5 C
30、L= 50 pF 2/ 9, 10, 11 39 ns CL= 15 pF 3/ 9 26 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC
31、 FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Limits Unit unless otherwise specified Min Max Propagation delay time clock to CCO tPLH6 RL2= 2 k (figure 4) CL= 50 pF 2/ 9, 10, 11 18 ns CL= 15 pF 3/
32、9 15 tPHL6 CL= 50 pF 2/ 9, 10, 11 27 ns CL= 15 pF 3/ 9 15 Propagation delay time CET or CEP to CCO tPLH7 CL= 50 pF 2/ 9, 10, 11 17 ns CL= 15 pF 3/ 9 15 tPHL7 CL= 50 pF 2/ 9, 10, 11 45 ns CL= 15 pF 3/ 9 25 Propagation delay time ACLR to any Q tPLH8 RL1= 5 k RL2= 2 k (figure 4) CL= 50 pF 2/ 9, 10, 11
33、N/A ns CL= 15 pF 3/ 9 N/A tPHL8 CL= 50 pF 2/ 9, 10, 11 45 ns CL= 15 pF 3/ 9 26 Setup time, A, B, C, D tS1 2/ 9, 10, 11 35 ns 3/ 9 22 Setup time, SCLR tS2 2/ 9, 10, 11 35 ns 3/ 9 20 Setup time, LOAD tS3 2/ 9, 10, 11 45 ns 3/ 9 30 Setup time, U/D tS4 2/ 9, 10, 11 45 ns 3/ 9 30 Setup time, CET , CEP tS
34、5 2/ 9, 10, 11 65 ns 3/ 9 32 Setup time, SCLR recovery time (inactive to clock) tS6 2/ 9, 10, 11 60 ns 3/ 9 30 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND
35、 MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Limits Unit unless otherwise specified Min Max Data hold tH 2/ 9, 10, 11 5 ns 3/ 9 0 C
36、lock pulse width tPW 2/ 9, 10, 11 37 ns 3/ 9 25 Enable time OE to any Q tZH RL1= 5 k RL2= 2 k (figure 4) CL= 50 pF 2/ 9, 10, 11 20 ns CL= 15 pF 3/ 9 11 Enable time OE to any clock tZL CL= 50 pF 2/ 9, 10, 11 34 ns CL= 15 pF 3/ 9 19 Disable time OE to any Q tHZ CL= 5 pF RL1= 5 k RL2= 2 k 2/ 9, 10, 11
37、22 ns 3/ 9 18 tLZ 2/ 9, 10, 11 36 ns 3/ 9 24 1/ Not more than one output should be shorted at a time, and the duration of the short circuit condition should not exceed one second. 2/ Supply voltage = +4.5 V to +5.5 V, operating temperature = -55C to +125. 3/ Supply voltage = +5.0 V, operating temper
38、ature = +25C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case Outline R, S, and 2 Termi
39、nal Number Terminal Symbol 1 U/ D 2 CP 3 A 4 B 5 C 6 D 7 CEP 8 ACLR 9 SCLR 10 GND 11 LOAD 12 CET 13 YD 14 YC 15 YB 16 YA 17 OE 18 CCO 19 RCO 20 VCC FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT
40、DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Mode INPUTS OUTPUTS Load CEP CET U/ D Async clear Sync clear OE 1/ D0 D1 D2 D3 CP Q0 Q1 Q2 Q3 RC Clock carry Clear (async) X X X 1 0 X 0 X X X X X 0 0 0 0 1 1 X X X 0 0 X 0 X X X
41、X X 0 0 0 0 0 2/ Clear (sync) X X X 1 1 0 0 X X X X . 0 0 0 0 1 1 X X X 0 1 0 0 X X X X . 0 0 0 0 0 2/ Load 0 X 1 X 1 1 0 X X X X . Qn = Dn1 1 0 X 0 0 1 1 0 0 0 0 0 . 0 0 0 0 0 2/ 0 X 0 1 1 1 0 1 1 1 1 . 1 1 1 1 0 2/ Count up 1 0 0 1 1 1 0 X X X X . Qn +1 3/ 4/ Count down 1 0 0 1 1 1 0 X X X X . Qn
42、-1 5/ 4/ Inhibit 1 0 1 X 1 1 0 X X X X NC NC 1 1 1 0 X 1 1 0 X X X X NC NC 1 1 1 1 X 1 1 0 X X X X . NC NC 1 Output disable X X X X X X 1 X X X X X Z Z Z Z NC NC = Clock low-to-high transition. X = Dont care. Dn = D0through D3input level prior to clock transition. Qn +1 = Next higher count in binary
43、 sequence. Qn -1 = Next lower count in binary sequence. NC = No change. NOTES: 1. Register performs at correct logic for any state of OE , but OE = 0 to view outputs. 2. Follows clock if CET = CEP = 0, otherwise remains high. 3. Low for one full clock cycle when maximum count is reached otherwise re
44、mains high. 4. Follows clock when RC = 0. 5. Low for one full clock cycle when minimum count is reached otherwise remains high. FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA
45、 LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO
46、 43218-3990 REVISION LEVEL D SHEET 11 DSCC FORM 2234 APR 97 Switch Matrix Parameter SW1 SW2 tPLHClosed Closed tPHLClosed Closed tZLOpen Closed tZHClosed Open tLZClosed Closed tHZClosed Closed FIGURE 4. Switching waveforms and test circuits. Provided by IHSNot for ResaleNo reproduction or networking
47、permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 12 DSCC FORM 2234 APR 97 FIGURE 4. Switching waveforms and test circuits - Continued. Provided by IHSNot for ResaleNo reproduction or networki
48、ng permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87544 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 13 DSCC FORM 2234 APR 97 NOTES: 1. Pulse generator for all pulses. 2. Rate 1.0 MHz; Z0= 50; tr 14 ns; tf 6.0 ns. 3. CLincludes probe and jig capacitance. 4. All diodes are 1N916 or 1N3064. FIGURE 4. Switching waveforms and test circuits -
