1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Delete vendor CAGE 27014. Change vendor CAGE 18714 to 34371. Technical changes in table I. Editorial changes throughout. 91-12-17 Michael A. Frye B Technical changes in table I. Update to new boilerplate. Delete vendor CAGE 04713. Editorial chang
2、es throughout. 94-11-07 Monica L. Poelking C Add notes to figure 4, switching waveforms and test circuit. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout. - jak 06-10-19 Thomas M. Hess D Update boilerplate paragraphs to the current MIL-PRF-3
3、8535 requirements. - LTG 13-08-29 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY James E. Nicklaus DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT D
4、RAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY Robert P. Evans MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, 14-STAGE BINARY COUNTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 87-11-25 REVISION LEVEL D SIZE
5、 A CAGE CODE 67268 5962-87680 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E552-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87680 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DS
6、CC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87680 01 E
7、 A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC4060 14-stage binary counter 1.2.2 Case outline(s). The case outline(s) are
8、 as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum rati
9、ngs. 1/ 2/ 3/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc Clamp diode current (IIK, IOK) 20 mA DC output diode current (per pin) (IOUT) 25 mA DC VCCor GND current (per pin) 50
10、 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C 1/ Stresses above the absolute maximum rating may cause permanen
11、t damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature r
12、ange of -55C to +125C. 4/ For TC= +100C to TC= +125C, derate linearly at 8 mW/C to 300 mW. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87680 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL
13、D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) . +2.0 V dc to +6.0 V dc Case operating temperature range (TC) -55C to +125C Input voltage range (VIN) . 0.0 V dc to VCC Output voltage range (VOUT) 0.0 V dc to VCCInput rise or fall time (tr, tf): VCC=
14、2.0 V . 0 to 1000 ns VCC= 4.5 V . 0 to 500 ns VCC= 6.0 V . 0 to 400 ns Minimum removal time, reset inactive to clock (trem): TC= +25C: VCC= 2.0 V . 160 ns VCC= 4.5 V . 32 ns VCC= 6.0 V . 27 ns TC= -55C to +125C: VCC= 2.0 V . 240 ns VCC= 4.5 V . 48 ns VCC= 6.0 V . 41 ns Minimum clock pulse width (tw1
15、): TC= +25C: VCC= 2.0 V . 90 ns VCC= 4.5 V . 18 ns VCC= 6.0 V . 15 ns TC= -55C to +125C: VCC= 2.0 V . 135 ns VCC= 4.5 V . 27 ns VCC= 6.0 V . 23 ns Minimum reset pulse width (tw2): TC= +25C: VCC= 2.0 V . 90 ns VCC= 4.5 V . 18 ns VCC= 6.0 V . 15 ns TC= -55C to +125C: VCC= 2.0 V . 135 ns VCC= 4.5 V . 2
16、7 ns VCC= 6.0 V . 23 ns Maximum clock frequency (fmax): TC= +25C: VCC= 2.0 V . 4 MHz minimum VCC= 4.5 V . 20 MHz minimum VCC= 6.0 V . 24 MHz minimum TC= -55C to +125C: VCC= 2.0 V . 2.6 MHz minimum VCC= 4.5 V . 13.0 MHz minimum VCC= 6.0 V . 15.0 MHz minimum Provided by IHSNot for ResaleNo reproductio
17、n or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87680 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specific
18、ation, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Speci
19、fication for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings.
20、(Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified
21、 herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available onl
22、ine at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201-2107). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence.
23、Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specifie
24、d herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved pro
25、gram plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not aff
26、ect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, a
27、ppendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram
28、shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87680
29、 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperatu
30、re range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PI
31、N listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance
32、 indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance.
33、A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufa
34、cturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of chang
35、e. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable requir
36、ed documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87680 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 RE
37、VISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max High level output voltage, Q4-Q10, Q12-Q14 VOH12/ VIN= VIHminimum or VILmaximum IOH= -20 A 2.
38、0 V 1, 2, 3 1.9 V 4.5 V 4.4 6.0 V 5.9 VIN= VIHminimum or VILmaximum IOH= -4.0 mA 4.5 V 3.7 VIN= VIHminimum or VILmaximum IOH= -5.2 mA 6.0 V 5.2 Low level output voltage, Q4-Q10, Q12-Q14 VOL12/ VIN= VIHminimum or VILmaximum IOL= +20 A 2.0 V 1, 2, 3 0.1 V 4.5 V 0.1 6.0 V 0.1 VIN= VIHminimum or VILmaxi
39、mum IOL= +4.0 mA 4.5 V 0.4 VIN= VIHminimum or VILmaximum IOL= +5.2 mA 6.0 V 0.4 High level output voltage, Osc OUT 1 VOH22/ 3/ VIN= VCCor GND IOH= -20 A 2.0 V 1, 2, 3 1.9 V 4.5 V 4.4 6.0 V 5.9 VIN= VCCor GND IOH= -2.6 mA 4.5 V 3.7 VIN= VCCor GND IOH= -3.3 mA 6.0 V 5.2 High level output voltage, Osc
40、OUT 2 VOH32/ 3/ VIN= VIHminimum or VILmaximum IOH= -3.2 mA 4.5 V 1, 2, 3 3.7 V VIN= VIHminimum or VILmaximum IOH= -4.2 mA 6.0 V 5.2 Low level output voltage, Osc OUT 1 VOL22/ 3/ VIN= VCCor GND IOL= +20 A 2.0 V 1, 2, 3 0.1 V 4.5 V 0.1 6.0 V 0.1 VIN= VCCor GND IOL= +2.6 mA 4.5 V 0.4 VIN= VCCor GND IOL
41、= +3.3 mA 6.0 V 0.4 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87680 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I.
42、 Electrical performance characteristics Continued. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max Low level output voltage, Osc OUT 2 VOL32/ 3/ VIN= VIHminimum or VILmaximum IOL= +3.2 mA 4.5 V 1, 2, 3 0.4 V VIN= VIHminimum or VILmaxim
43、um IOL= +4.2 mA 6.0 V 0.4 High level input voltage VIH4/ 2.0 V 1, 2, 3 1.5 V 4.5 V 3.15 6.0 V 4.2 Low level input voltage VIL4/ 2.0 V 1, 2, 3 0.5 V 4.5 V 1.35 6.0 V 1.8 Input capacitance CINTC+25C, see 4.3.1c GND 4 10 pF Quiescent supply current ICCVIN= VCCor GND 6.0 V 1, 2, 3 160 A Input leakage cu
44、rrent IINVIN= VCCor GND 6.0 V 1, 2, 3 1 A Functional tests See 4.3.1d 7, 8 Propagation delay time, CLOCK to Q4 tPHL1, tPLH15/ CL= 50 pF minimum See figure 4 2.0 V 9 530 ns 10, 11 795 4.5 V 9 106 10, 11 159 6.0 V 9 90 10, 11 135 Propagation delay time, Qn to Qn + 1 tPHL2, tPLH25/ CL= 50 pF minimum Se
45、e figure 4 2.0 V 9 125 ns 10, 11 190 4.5 V 9 25 10, 11 38 6.0 V 9 21 10, 11 32 Propagation delay time, RESET to any Q tPHL35/ CL= 50 pF minimum See figure 4 2.0 V 9 240 ns 10, 11 360 4.5 V 9 48 10, 11 72 6.0 V 9 41 10, 11 61 See footnotes on next sheet. Provided by IHSNot for ResaleNo reproduction o
46、r networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87680 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ 55C TC +125C un
47、less otherwise specified VCCGroup A subgroups Limits Unit Min Max Transition time tTHL, tTLH6/ CL= 50 pF minimum See figure 4 2.0 V 9 75 ns 10, 11 110 4.5 V 9 15 10, 11 22 6.0 V 9 13 10, 11 19 1/ For power supply of 5.0 V 10 percent, the worst case output voltages (VOHand VOL) occur for high-speed C
48、MOS at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at VCC= 5.5 V is 3.85 V). The worst case leakage currents (IINand ICC) occur for CMOS at the higher voltage, so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 100 pF, determines the no load dynamic power consumption, PD= CPDVCC2 f + ICCVCC, and the no load dynamic current consumption, IS= CPDVCCf + ICC. 2/ VCC= 2.0 V and VCC= 6.0 V shall be guaranteed,
