1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes to recommended operating conditions and table I. Editorial changes throughout. 95-05-03 M. A. Frye B Changes in accordance with NOR 5962-R124-96. sr 96-05-10 Michael A. Frye C Add footnotes to para. 1.2.1, 1.3 and Table I. Update to refle
2、ct latest changes in format and requirements. Editorial changes throughout. les 05-09-12 Thomas M. Hess THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Rick C. Officer DEFEN
3、SE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, OCTAL GENERAL INTERFACE BUS TRANSCEIVER, AND AGENCIES OF THE DEPAR
4、TMENT OF DEFENSE DRAWING APPROVAL DATE 89-07-05 MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67628 5962-89680 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E510-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW
5、ING SIZE A 5962-89680 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.
6、2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89680 01 R X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identify the circuit function as follows: Device type Generic number Ci
7、rcuit function 01 55ALS160 1/ Octal general purpose interface bus transceiver 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 dual-in-line S GDFP2-F20 or CDFP3-F20 20 fl
8、at 2 CQCC1-N20 20 square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage (VCC) +7.0 V dc Input voltage +5.5 V dc Low level driver output current . 100 mA Storage temperature -65C to +150C Continuous t
9、otal dissipation TA +25C 2/ . 1375 mW Lead temperature (soldering, 10 seconds) +300C Junction temperature (TJ) +150C 1.4 Recommended operating conditions. Supply voltage range (VCC) 4.75 V dc minimum to 5.25 V dc maximum Minimum high level input voltage (VIH): TE and PE, TA= -55C to +125C . 2.0 V dc
10、 Bus and terminal, TA= +25C, +125C . 2.0 V dc Bus and terminal, TA= -55C 2.1 V dc _ 1/ The manufacturer cannot warranty latch up performance if the Bus I/O pins (device pins 2-9) are subjected to voltages below 0V (negative w/respect to ground). While negative voltage on these pins is not a typical
11、condition, special care must be exercised to assure that the Bus pins will not be subjected to a negative voltage. Otherwise, the device can latch up causing it to become inoperable and/or causing permanent damage to the device. 2/ For operation above TA= +25C, derate at the rate of 11.0 mW/C. Provi
12、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89680 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Maxim
13、um low level input voltage (VIL): TE and PE, TA= -55C to +125C . 0.8 V dc Bus and terminal, TA= -55C, +25C 0.8 V dc Bus and terminal, TA= +125C . 0.7 V dc Minimum high level output current (IOH): Bus ports with pull-ups active (VCC= 5.0 V dc) -5.2 mA Terminal ports . -800 A Maximum low level output
14、current (IOL): Bus ports, TA= +25C, +125C . 48 mA Bus ports, TA= -55C 24 mA Terminal ports . 16 mA Ambient operating temperature range (TA). -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
15、 of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDAR
16、DS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available on
17、line at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified he
18、rein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. The Institute of Electrical and Electronics Engineers (IEEE) IEEE Standard 488 - STANDARD DIGITAL INTERFACE FOR PROGRAMMABLE INSTRUMENTATION (Copies of this document are available online at or from
19、the IEEE Operations Center, 445 Hoes Lane, Piscataway, New Jersey 08854-1331). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable law
20、s and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89680 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FO
21、RM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified a
22、nd qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in th
23、e Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is require
24、d to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 T
25、erminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.2.4 Test circuits and switching waveforms. The test circuits and switching waveforms shall be as specified on figure 3 3.3 Electrical performance
26、 characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table
27、II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire
28、 SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance
29、indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply
30、 in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certif
31、icate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs
32、 agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license
33、from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89680 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroupsDe
34、vice type Limits Unit Min Max 1, 2 2.7 High level output voltage (terminal) VOHVCC= 4.75 V, TE at 0.8 V IOH= -0.8 mA 3 All 2.5 V 1, 2 2.5 High level output voltage (bus) 2/ VCC= 4.75 V, PE and TE at 2.0 V IOH= -5.2 mA 3 2.0 Low level output voltage (terminal) VOLVCC= 4.75 V, TE at 0.8 V IOL= 16 mA 1
35、, 2, 3 All 0.5 V IOL= 48 mA 1, 2 0.5 Low level output voltage (bus) 2/ VCC= 4.75 V, TE at 2.0 V IOL= 24 mA 3 0.55 Input clamp voltage VICVCC= 4.75 V, II= -18 mA 1, 2, 3 All -1.5 V 1, 3 0.4 Bus hysteresis (VT+- VT-) VHYSVCC= 5 V 2 All 0.25 V Voltage at bus port VI/OVCC= 5 V, II(bus)= 0 mA 1, 2, 3 All
36、 2.5 3.7 V (driver disabled) (bus) VCC= 5 V, II(bus)= -12 mA -1.5 Current into bus port II/OVCC= 5 V, VI(bus)= -1.5 V to 0.4 V 1, 2, 3 All -1.3 mA (power on, driver disabled) (bus) VCC= 5 V, VI(bus)= 0.4 V to 2.5 V -3.2 0 CC= 5 V, VI(bus)= 2.5 V to 3.7 V -3.2 2.5 CC= 5 V, VI(bus)= 3.7 V to 5 V 0 2.5
37、 CC= 5 V, VI(bus)= 5 V to 5.5 V 0.7 2.5 Current into bus port (power off) VCC= 0.0 V, VI(bus)= 0.0 V to 2.5 V 40 A Input current at maximum input voltage (terminal) IIH1VI= 5.5 V, VCC= 5.25 V 1, 2, 3 All 100 A High level input current (terminal, PE, or TE) IIH2VI=2.7 V, VCC= 5.25 V 1, 2, 3 All 20 A
38、Low level input current (terminal, PE, or TE) IILVI=0.5 V, VCC= 5.25 V 1, 2, 3 All -100 A Short circuit output current (terminal) IOSVCC= 5.25 V 1, 2, 3 All -15 -75 mA Short circuit output current (bus) -25 -125 Supply current (terminal) ICCVCC= 5.25 V, no load, outputs low 1, 2, 3 All 56 mA Supply
39、current (bus) and enabled 85 Functional tests FT See 4.3.1c 3/ 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89680 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218
40、-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroupsDevice type Limits Unit Min Max Propagation delay time, tPLH1 VCC= 4.75 V to 5.25 V, 9 All 17 ns from
41、terminal to bus R1= R2= 500, 10, 11 20 tPHL1CL= 50 pF, 9 14 See figure 3 10, 11 16 Propagation delay time, tPLH2 9 All 15 ns from bus to terminal 10, 11 18 tPHL29 15 10, 11 18 Output enable time, tPZH1 9 All 30 ns from TE to bus 10, 11 41 tPZL19 28 10, 11 34 Output disable time, tPHZ19 All 14 ns fro
42、m TE to bus 10, 11 16 tPLZ19 19 10, 11 24 Output enable time, tPZH2 9 All 36 ns from TE to terminal 10, 11 50 tPZL29 26 10, 11 30 Output disable time, tPHZ29 All 18 ns from TE to terminal 10, 11 23 tPLZ29 24 10, 11 31 Output pull-up enable time, ten9 All 24 ns from PE to bus 10, 11 25 Output pull-up
43、 disable tdis9 All 16 ns time 10, 11 20 1/ The manufacturer cannot warranty latch up performance if the Bus I/O pins (device pins 2-9) are subjected to voltages below 0V (negative w/respect to ground). While negative voltage on these pins is not a typical condition, special care must be exercised to
44、 assure that the Bus pins will not be subjected to a negative voltage. Otherwise, the device can latch up causing it to become inoperable and/or causing permanent damage to the device. 2/ May not meet IEEE 488 standard. 3/ Functional test shall be conducted at input test conditions of GND VIL VOLand
45、 VOH VIH VCC. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89680 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines R, S, 2
46、 Terminal number Terminal symbol 1 TE 2 B1 3 B2 4 B3 5 B4 6 B5 7 B6 8 B7 9 B8 10 GND 11 PE 12 D8 13 D7 14 D6 15 D5 16 D4 17 D3 18 D2 19 D1 20 VCCFIGURE 1. Terminal connections. Each driver: Each receiver: Inputs Output Inputs Output D TE PE B D TE PE D H H H H L L X L L H X L H L X H H X L *Z X H X
47、Z X L X *Z H = High L = Low Z = High impedance * = This is the high impedance state of normal 3-state output modified by the internal resistors to VCCand ground. FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCI
48、RCUIT DRAWING SIZE A 5962-89680 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Terminal to bus propagation delay times. Bus to terminal propagation delay times. TE to bus enable and disable times. FIGURE 3. Test circuits and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A
