1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 02. Technical changes in table I. Editorial changes throughout. 94-09-21 M. L. Poelking B Add QD device criteria. Add vendor CAGE 3V146. Update boilerplate to latest MIL-PRF-38535 requirements. - CFS 04-06-14 Thomas M. Hess REV SH
2、ET REV B B B B B B B SHEET 15 16 17 18 19 20 21 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Christopher A. Rauch DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY William K. Heckman COLUMBUS, OHIO 43218-3990 h
3、ttp:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY William K. Heckman MICROCIRCUIT, DIGITAL, CHMOS, 16-BIT AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 90-09-27 MICROCONTROLLER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268
4、 5962-89982 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E295-04 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89982 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2
5、234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89982 01 Z X Drawin
6、g number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 80C196KB 12 MHz CHMOS 16-bit microcontroller 02 80C196KB-12 12 MHz CHMOS 16-bit microcon
7、troller 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Z CMGA3-P68 68 Pin grid array Y See figure 1 68 Leaded chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535,
8、appendix A. 1.3 Absolute maximum ratings. Supply voltage range (VCC) 4.5 V dc to 5.5 V dc Voltage on any pin with respect to ground. -0.5 V to +7.0 V Storage temperature range -65C to +150C Case operating temperature range (TC). -55C to +125C Power dissipation (PD) . 1.5 W 1/ Lead temperature (solde
9、ring 10 seconds). 265C Junction temperature (TJ) 150C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 1.4 Recommended operating conditions. Case operating temperature range (TC). -55C to +125C 2/ Supply voltage range (VCC) 4.5 V dc to 5.5 V dc Digital circuit ground (VSS) . 0.0 V dc Anal
10、og supply voltage (VREF) . 4.5 V dc to 5.5 V dc Frequency of operation (fO) 3.5 MHz to 12 MHz High level input voltage: Excluding XTAL1, RESET (VIH) 1.9 V dc to 6.0 V dc XTAL1 (VIH1). 3.15 V dc to 6.0 V dc RESET (VIH2) 2.2 V dc to 6.0 V dc Low level input voltage (VIL). -0.5 V dc to 0.8 V dc _ 1/ Mu
11、st withstand the added PDdue to short circuit test; e.g., IOS. 2/ Case temperatures are “instant on”. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89982 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-
12、3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these docume
13、nts are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Compo
14、nent Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Docum
15、ent Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable law
16、s and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by
17、a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance wit
18、h MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certificatio
19、n mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the qualifying activity.
20、 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and on figure 1. 3.2.2 Terminal connections. The termin
21、al connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance charact
22、eristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The ele
23、ctrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89982 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234
24、 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the
25、 manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certifica
26、tion mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q“ or “QML“ certification mark. 3.6 Certific
27、ate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manuf
28、acturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of chan
29、ge. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be m
30、ade available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89982 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR
31、97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Input low voltage VILAll -0.5 0.8 V 01 0.2VCC+ 1.0 VCC+ 0.5 Input high voltage (all except RESET and XTAL1) VIH02 0
32、.2VCC+ 1.1 VCC+ 0.5 V Input high voltage, XTAL1 VIH1All 0.7VCCVCC+ 0.5 V Input high voltage on RESET VIH2All 2.2 VCC+ 0.5 V IOL= 200 A 0.3 IOL= 3.2 mA 0.45 Output low voltage VOLIOL= 7.0 mA All 1.5 V IOH= -200 A VCC 0.3 IOH= -3.2 mA VCC 0.7 Output high voltage (standard outputs) VOHIOH= -7.0 mA All
33、VCC 1.5 V IOH= -10 A VCC 0.3 IOH= -30 A VCC 0.7 Output high voltage (quasi-bidirectional outputs) VOH1IOH= -60 A All VCC 1.5 V Input leakage current (standard inputs) ILI0.0 V VIN VCC 0.3 V All 10 A Input leakage current (Port 0) ILI10.0 V VIN VREFAll 3 A 01 -650 1 to 0 transition current (QBD) pins
34、 ITLVIN= 2.0 V 02 -800 A Logical 0 input current (QBD) pins IILVIN= 0.45 V All -50 A 01 -850 Logical 0 input current in RESET (ALE, RD, WR, BHE, INST, P2.0) IIL1VIN= 0.45 V 2/ 02 -7 mA Active mode current RESET ICCXTAL1 = 12 MHz VCC= VPP= VREF= 5.5 V All 60 mA A/D converter reference current IREFXTA
35、L1 = 12 MHz VCC= VPP= VREF= 5.5 V 1, 2, 3 All 5 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89982 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL
36、B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max 01 22 Idle mode current IIDLEXTAL1 = 12 MHz VCC= VPP= VREF= 5.5 V 02 25 mA
37、 01 22 Active mode current ICC1XTAL1 = 3.5 MHz 02 30 mA Power down mode current IPDXTAL1 = 12 MHz VCC= VPP= VREF= 5.5 V 1, 2, 3 All 50 A Reset pull-up resistor RRST4, 5, 6 All 6K 50K Pin capacitance (any pin to VSS) CSfTEST= 1.0 MHz See 4.3.1c 4 All 10 pF Address valid to READY setup tAVYVAll 2tOSC-
38、 85 ns ALE low to READY setup tLLYVtOSC- 75 ns Non READY time tYLYHAll No upper limit ns READY hold after CLKOUT low tCYLXAll 0 tOSC- 30 ns READY hold after ALE low tLLYXtOSC- 15 2tOSC- 40 ns Address valid to BUS WIDTH setup tAVGVAll 2tOSC- 85 ns ALE low to BUS WIDTH setup tLLGVtOSC- 70 ns BUS WIDTH
39、 hold after CLKOUT low tCLGXAll 0 ns Address valid to input data valid tAVDV3tOSC- 67 ns RD active to input data valid tRLDVAll tOSC- 23 ns CLKOUT low to input data valid tCLDVtOSC- 50 ns End of RD to input data float tRHDZAll tOSC- 20 ns Data hold after RD inactive tRXDX0 ns Frequency on XTAL1 fXTA
40、LAll 3.5 12 MHz 1/fXTALtOSCCapacitance load on all pins = 100 pF, rise and fall time = 10 ns, fOSC= 12 MHz, See figure 4 9, 10, 11 All 83 286 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW
41、ING SIZE A 5962-89982 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type
42、Limits Unit Min Max 01 35 110 XTAL1 high to CLKOUT high or low tXHCH3/ 02 20 110 ns CLKOUT cycle time tCLCL4/ All 2tOSCns CLKOUT high period tCHCLAll tOSC- 10 tOSC+ 10 ns 01 -5 15 CLKOUT falling edge to ALE rising tCLLH02 -10 10 ns ALE high period tLHLLAll tOSC- 12 tOSC+ 12 ns Address setup to ALE f
43、alling edge tAVLLtOSC- 20 ns Address hold after ALE falling edge tLLAXAll tOSC- 40 ns ALE falling edge to RD falling edge tLLRLtOSC- 40 ns 01 5 30 RD low to CLKOUT falling edge tRLCL02 4 25 ns ALE falling edge to CLKOUT rising tLLCHAll -15 15 ns ALE cycle time tLHLH4/ All 4tOSCns RD low period tRLRH
44、All tOSC- 5 ns RD rising edge to rising edge tRHLH5/ All tOSCtOSC+ 25 ns RD low to address float tRLAZAll 10 ns ALE falling edge to WR falling edge tLLWLtOSC- 10 ns CLKOUT low to WR falling edge tCLWLAll 0 25 ns Data stable to WR rising edge tQVWHtOSC- 23 ns 01 tOSC- 10 Data hold after WR rising edg
45、e tWHQX02 tOSC- 15 ns 01 tOSC- 10 tOSC+ 15 WR rising edge to ALE rising edge tWHLH5/ 02 tOSC- 15 tOSC+ 10 ns 01 tOSC- 10 BHE, INST hold after WR rising edge tWHBXCapacitance load on all pins = 100 pF, rise and fall time = 10 ns, fOSC= 12 MHz, See figure 4 9, 10, 11 02 tOSC- 15 ns See footnotes at en
46、d of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89982 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance charac
47、teristics - Continued. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Oscillator frequency 1/tXLXLAll 3.5 12.0 MHz01 -10 10 CLKOUT high to WR rising edge tCHWH02 -5 15 ns WR low period tWLWHAll tOSC- 30 ns Oscillat
48、or period tOP83 286 High time tHT32 ns Low time tLTAll Rise time tRT10 ns Fall time tFTSerial port clock period (BRR 8002H) tXLXL3/ All 6tOSCns Serial port clock falling edge to rising edge (BRR 8002H) tXLXH3/ All 4tOSC 50 4tOSC+ 50 ns Output data setup to clock rising edge tQVXH3/ All 2tOSC- 50 ns Output data hold after clock rising edge tXHQX3/ All 2tOSC- 50 ns Next output data valid after clock rising edge tXHQV3/ All 2tOSC+ 50 ns Serial port clock period (BRR = 8001H) tXLXL3/ All 4tOSCns Serial port clock falling edge to rising edge (BRR = 8001H) tXLXH3/ All 2tOSC 50 2tOSC+ 50 ns In
