1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - drw 04-12-15 Raymond Monnin REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Dan Wonnell DEFENSE SUPPL
2、Y CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin MICROCIRCUIT, DIGITAL-LINEAR, DUAL, 12-BIT AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPR
3、OVAL DATE 99-05-27 D/A CONVERTERS, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-90785 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E052-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 59
4、62-90785 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of c
5、ase outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90785 01 M L A Federal stock class des
6、ignator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropr
7、iate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types identify the circuit function as follows: Device type Generic
8、 number Circuit function 01 AD7247A Dual, CMOS, 12-bit D/A converters 02 AD7237A Dual, CMOS, 12-bit D/A converters 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor
9、 self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 and as follows: Outline le
10、tter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking perm
11、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90785 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. VDDto GND (device type 01) . -0.3 V to +17 V dc VDDto AGND, DGND (device type 02) -
12、0.3 V to +17 V dc VDDto VSS-0.3 V to +34 V dc AGND to DGND (device type 02) -0.3 V, VDD+0.3V VOUTA, VOUTBto AGND 1/ . VSS- 0.3 V to VDD+ 0.3 V REF OUT to AGND 1/ . 0 V to VDDREF IN to AGND . -0.3 V to VDD+ 0.3 V Digital inputs to DGND. -0.3 V to VDD+ 0.3 V Storage temperature range -65C 10 +150C Lea
13、d temperature (soldering, 10 sec.). +300C Power dissipation to +75C 1000 mW, derate above +75C by 10 mW/C Thermal resistance, junction-to-ambient (JA) 120C/W Thermal resistance, junction-to-case (JC). 35C/W 1.4 Recommended operating conditions. Ambient operating temperature range (TA) -55C to +125C
14、2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
15、 DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS
16、MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4
17、D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption
18、has been obtained. _ 1/ The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90785 DEFENSE SUPPLY
19、 CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Qu
20、ality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design
21、, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 h
22、erein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical pe
23、rformance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each
24、 subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not m
25、arking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/complianc
26、e mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall
27、 be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein).
28、 The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535,
29、appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for de
30、vice class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring ac
31、tivity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
32、 microcircuit group number 56 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90785 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM
33、2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxResolution RES 1, 2, 3 All 12 Bits Relative accuracy RA 2/ 1, 2, 3 All -0.5 +0.5 LSB Differential non-linearity DNL Must be
34、monotonic 2/ 1, 2, 3 All -0.9 +0.9 LSB Unipolar offset error UNI DAC latch contents all 0s 3/ 1, 2, 3 All -4.0 +4.0 LSB Bipolar zero error BZEVDD= 11.4 V, VSS= -11.4 V and range = 5 V VSS= -15 V DAC latch contents 1000 0000 0000 1, 2, 3 All -6.0 +6.0 LSB Full scale error AE4/ 1, 2, 3 All -6.0 +6.0 L
35、SB Reference output REFOUT 5/ 1, 2, 3 All 4.95 5.05 V Reference temperature coefficient REF TC 6/ 1, 2, 3 All -25 +25 PPM/C Reference load change REF REF OUT vs I reference load current change (0 - 100 mA) 1, 2, 3 All -1.0 mV Reference input range REF IN 7/ 1, 2, 3 All 4.75 5.25 V Reference input cu
36、rrent IINREF IN = 5.0 V 1, 2, 3 All -5.0 +5.0 A Digital input current IINHVIN= VDD1, 2, 3 All -10 +10 A (control inputs) IINLVIN= 0 -150 Digital input current (data inputs) IINVIN= 0 V to VDD1, 2, 3 All -10 +10 A Digital input high voltage VINH1, 2, 3 All 2.4 V Digital input low voltage VINL1, 2, 3
37、All 0.8 V Input capacitance CINsee 4.4.1c 4 All 8 pF Output range resistors RR1, 2, 3 All 15 30 k Output voltage ranges VOUTVSS= 0 V (pin strappable) 1, 2, 3 All +5 V +10 VSS= -15 V (pin strappable) -5 +5 Power supply current IDDOutputs unloaded 1, 2, 3 All 15 mA ISSOutputs unloaded (dual supplies)
38、+5 Functional tests FT see 4.4.1d 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90785 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET
39、6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxCS to WR setup time t1see figure 3 8/ 9, 10, 11 All 0 ns CS to WR hold time t2see figure 3 9, 10, 11
40、 All 0 ns WR pulse width t3see figure 3 9, 10, 11 All 100 ns Data valid to write setup time t4see figure 3 9, 10, 11 All 80 ns Data valid to write setup time t5see figure 3 9, 10, 11 All 10 ns Address to WR setup time t6see figure 3 9, 10, 11 02 0 ns Address to WR hold time t7see figure 3 9, 10, 11
41、02 0 ns LDAC pulse width t8see figure 3 9, 10, 11 02 100 ns 1/ VDD= +12 V 5% or +15 V 15%, VSS= 0 V or -12 V 5% or -15 V 5%, GND = 0 V, RL= 2 k, CL= 100 pF. Parts are guaranteed over this supply range. Individual tests are performed using known worst case supply conditions. 2/ VDD= +11.4 V, VSS= -11
42、.4 V and Range = 5 V; VDD= +14.25 V, VSS= -14.25 V and range = +10 V; VDD= +11.4 V, VSS= 0 V and range = +5 V. 3/ VDD= +14.25 V, VSS= -14.25 V and Range = 10 V; VDD= +15.75 V, VSS= 0 V and range = +10 V; VDD= +11.4 V, VSS= 0 V and range = +5 V; VDD= +11.4 V, VSS= -11.4 V and Range = 5 V 4/ Measured
43、with respect to REF IN and includes unipolar/bipolar offset error. VDD= +11.4 V, VSS= -11.4 V and Range = 5 V; VDD= +14.25 V, VSS= -14.25 V and range = +10 V; VDD= +15.75 V, VSS= 0 V and range = +10 V; VDD= +11.4 V, VSS= 0 V and range = +5 V. 5/ Reference output voltage shall not change more than 0.
44、39% from its original value, over the operating life of the device. 6/ If not tested, shall be guaranteed to the limits specified in table I. 7/ This is a recommended input range. Testing is done with nominal value of 5.0 V. 8/ All input signals are specified with tR= tF= 5 ns (10% to 90% of 5 V) an
45、d timed from a voltage level of 1.6 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90785 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Device type
46、 01 02 Case outline L Terminal number Terminal symbol 1 REF OUT REF INA 2 ROFSBREF OUT 3 VOUTBREF INB 4 DB11 ROFSB5 DB10 VOUTB6 GND AGND 7 DB9 DB7 8 DB8 DB6 9 DB7 DB5 10 DB6 DB4 11 DB5 DB3 12 DB4 GND 13 DB3 DB2 14 DB2 DB1 15 DB1 DB0 16 DB0 A0 17 CSB A1 18 CSA CS 19 WR WR 20 VDDLDAC 21 VOUTAVDD22 VSS
47、 OUTA23 ROFSAVSS24 REF IN ROFSAFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90785 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM
48、 2234 APR 97 Device type 01 CSA CSB WR Function X X 1 No data transfer 1 1 X No data transfer 0 1 0 DAC A latch transparent 1 0 0 DAC B latch transparent 0 0 0 Both DAC latches transparent X = Dont care Device type 02 CS WR A1 A0 LDAC Function 1 X X X 1 No data transfer X 1 X X 1 No data transfer 0 0 0 0 1 DAC A LS input latch transparent 0 0 0 1 1 DAC A MS input latch transparent 0 0 1 0 1 DAC B LS input latch transparent 0 0 1 1 1 DAC B MS input latch transparent 1 1 X X 0 DAC A and DAC B latches updated simultaneously from the respective input latches
