1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated to current boilerplate requirements. lhl 12-09-14 Charles F. Saffle REV SHEET REV A A SHEET 15 16 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND M
2、ARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Rajesh Pithadia APPROVED BY Michael Frye MICROCIRCUIT, MEMORY, DIGITAL, BICMOS, ONE TIME PROGRAM
3、MABLE, PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-02-12 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-92338 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E456-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD
4、MICROCIRCUIT DRAWING SIZE A 5962-92338 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device clas
5、s V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 92338 01 M R A Feder
6、al stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are mar
7、ked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as foll
8、ows: Device type Generic number Circuit function Access time 01, 05 16L8 16-input 8-output AND-OR invert logic array 10, 7 ns 02, 06 16R8 16-input 8-output registered AND-OR invert logic array 10, 7 ns 03, 07 16R6 16-input 6-output registered AND-OR invert logic array 10, 7 ns 04, 08 16R4 16-input 4
9、-output registered AND-OR invert logic array 10, 7 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compl
10、iant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R
11、GDIP1-T20 or CDIP2-T20 20 Dual-in line S GDFP2-F20 or CDFP3-F20 20 Flat pack X CQCC2-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo rep
12、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92338 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range to ground potential (VCC) -0.5 V dc to +
13、7.0 V dc DC voltage applied to the outputs in the high Z state . -0.5 V dc to VCC +0.5 V DC input voltage . -1.2 V dc to VCC +0.5 V DC input current . -30 mA to +5 mA Maximum power dissipation . 1.0 W 2/ Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC) . See
14、 MIL-STD-1835 Junction temperature (TJ) . +175C Storage temperature range -65C to +150C Temperature under bias . -55C to +125C 1.4 Recommended operating conditions. Supply voltage VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0 V dc Input high voltage (VIH) . 2.0 V dc minimum In
15、put low voltage (VIL) . 0.8 V dc maximum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless othe
16、rwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD
17、-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Stand
18、ardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documen
19、ts cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201). 2.3 Order of precedence. In
20、 the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum
21、rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PD due to short circuit test (e.g., ISC). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH
22、S-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92338 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specifi
23、ed herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN c
24、lass level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outli
25、ne(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devi
26、ces for contracts involving no altered item drawing shall be as specified on figure 2. When required in screening (see 4.2 herein), or qualification conformance inspection groups A, B, C, or D (see 4.3 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percen
27、t of the total number of gates shall be programmed or at least 25 percent of the total number of gates to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics
28、 and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test
29、requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Verification of programmability. When specified, devices shall be verified as programmed (see 4.5 herein) to the specified pattern. As a minimum, verification shall consist o
30、f performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.6 Processing options. Since the device is capable of being programmed by either
31、the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 3.6.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 a
32、nd table II. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.6.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered
33、item drawing, shall be satisfied by the manufacturer prior to delivery. 3.7 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, th
34、e manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, app
35、endix A. 3.7.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.8 Certificate of compliance. For device classes Q an
36、d V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supp
37、ly in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or
38、for device class M, the requirements of MIL-PRF-38535, appendix A and herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92338 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSC
39、C FORM 2234 APR 97 3.9 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.10 Notification of change for devic
40、e class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.11 Verification and review for device class M. For device class M, DLA Land and Maritime, D
41、LA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.12 Microcircuit group assignment for device class M. Device cl
42、ass M devices covered by this drawing shall be in microcircuit group number 131 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92338 DLA LAND AND MARITIME COLUMBUS, OHIO 4321
43、8-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Output high voltage VOH VCC = 4.5 V, IOH = -2.0 mA VIN = VIH, VIL 1
44、, 2, 3 All 2.4 V Output low voltage VOL VCC = 4.5 V, IOL = 12.0 mA VIN = VIH, VIL 1, 2, 3 All 0.5 V Input high voltage 1/ VIH 1, 2, 3 All 2.0 V Input low voltage 1/ VIL 1, 2, 3 All 0.8 V Input leakage current 2/ IIX VCC = 5.5 V VIN = 0.4 V to 2.7 V 1, 2, 3 All -250 +50 A Maximum input current II VCC
45、 = 5.5 V, VIN = 5.5 V 1, 2, 3 All 1 mA Output leakage current 2/ IOZ VOUT = VCC to VSS, VCC = 5.5 V 1, 2, 3 All -100 +100 A Output short circuit current 3/ 4/ ISC VCC = 5.5 V, VOUT = 0.5 V 1, 2, 3 All -30 -130 mA Power supply current ICC VCC = 5.5 V, IOUT = 0 mA, VIN = GND 1, 2, 3 All 180 mA Input c
46、apacitance 4/ CIN VCC = 5.0 V, VIN = 0 V, TA = +25C, f = 1 MHz, (see 4.4.1f) 4 All 10 pF Output capacitance 4/ COUT VCC = 5.0 V, VOUT = 0 V, TA = +25C, f = 1 MHz (see 4.4.1f) 4 All 10 pF Functional testing See 4.4.1c 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproductio
47、n or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92338 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5
48、V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Input or feedback to nonregistered output tPD See figures 3 and 4 5/ 9,10,11 01, 03, 04 2 10 ns 05,0 7, 08 2 7 Input to output enable tEA 9,10,11 01, 03, 04 2 10 ns 05, 07, 08 2 7 Input to output disable delay 6/ tER 9,10,11 01, 03, 04 2 10 ns 05, 07, 08 2 7 OE to output enable tPZX 9,10,11 02, 03, 04 2 10 ns 06, 07, 08 2 7 OE to output disable 5/ tPXZ 9,10,11 02, 03, 04 2 10 ns 06, 07, 08 2 7 Clock to output tCO 9,10,11 02, 03, 04 2 7 ns 06, 07, 08 2 6 Skew between registered ou
