1、BRITISH STANDARDBS EN 62258-5:2006Semiconductor die products Part 5: Requirements for information concerning electrical simulationThe European Standard EN 62258-5:2006 has the status of a British StandardICS 31.080.99g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54
2、g54g44g50g49g3g40g59g38g40g51g55g3g36g54g3g51g40g53g48g44g55g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43g55g3g47g36g58BS EN 62258-5:2006This British Standard was published under the authority of the Standards Policy and Strategy Committee on 30 November 2006 BSI 2006ISBN 0 580 49608 2National forewor
3、dThis British Standard was published by BSI. It is the UK implementation of EN 62258-5:2006. It is identical with IEC 62258-5:2006. It supersedes PD ES 59008-4-4:2000, which will be withdrawn on 1 September 2009.The UK participation in its preparation was entrusted to Technical Committee EPL/47, Sem
4、iconductors. A list of organizations represented on EPL/47 can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application.Compliance with a British Standard cannot confer immunity
5、from legal obligations.Amendments issued since publicationAmd. No. Date CommentsEUROPEAN STANDARD EN 62258-5 NORME EUROPENNE EUROPISCHE NORM September 2006 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrote
6、chnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2006 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 62258-5:2006 E ICS 31.080.99 Supersedes ES 59008-4-4:1999English version Semiconductor die products P
7、art 5: Requirements for information concerning electrical simulation (IEC 62258-5:2006) Produits de matrice de semi-conducteur Partie 5: Exigences pour linformation concernant la simulation lectrique (CEI 62258-5:2006) Halbleiter-Chip-Erzeugnisse Teil 5: Anforderungen fr Angaben hinsichtlich der ele
8、ktrischen Simulation (IEC 62258-5:2006) This European Standard was approved by CENELEC on 2006-09-01. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteratio
9、n. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by transl
10、ation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Cyprus, the Czech Republic, Denmark, Estonia, Finland, Fran
11、ce, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom. EN 62258-5:2006 2 Foreword The text of document 47/1869/FDIS, future edition 1 of IE
12、C 62258-5, prepared by IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 62258-5 on 2006-09-01. This standard is to be used in conjunction with EN 62258-1 and EN 62258-2. The following dates were fixed: latest date by which the EN has
13、to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2007-06-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2009-09-01 Annex ZA has been added by CENELEC. _ Endorsement notice The text of the I
14、nternational Standard IEC 62258-5:2006 was approved by CENELEC as a European Standard without any modification. _ 3 EN 62258-5:2006 CONTENTS INTRODUCTION 4 1 Scope 5 2 Normative references .5 3 Terms and definitions.5 4 General5 5 Requirements for information on electrical simulation models6 5.1 Inf
15、ormation on the electrical simulation model6 5.2 Information on device connectivity .7 5.3 Information on the timing simulation model 7 5.4 Information on connection redistribution.7 5.5 Information on package terminals 8 Annex A (informative) Supporting information.9 Annex ZA (normative) Normative
16、references to international publications with their corresponding European publications .12 Bibliography .11 EN 62258-5:2006 4 INTRODUCTION This standard is based on the work carried out in the ESPRIT 4thFramework project GOODDIE which resulted in the publication of the ES 59008 series of European s
17、pecifications. Organisations that helped prepare this part of IEC 62258 includes the ESPRIT ENCAST project, the Die Products Consortium, JEITA, JEDEC and ZVEI. 5 EN 62258-5:2006 SEMICONDUCTOR DIE PRODUCTS Part 5: Requirements for information concerning electrical simulation 1 Scope This part of IEC
18、62258 has been developed to facilitate the production, supply and use of semiconductor die products, including: wafers; singulated bare die; die and wafers with attached connection structures; minimally or partially encapsulated die and wafers. This part of IEC 62258 specifies the information requir
19、ed to facilitate the use of electrical data and models for simulation of the electrical behaviour and verification of the correct functionality of electronic systems that include bare semiconductor die, with or without connection structures, and/or minimally packaged semiconductor die. It is intende
20、d to assist all those involved in the supply chain for die devices to comply with the requirements of IEC 62258-1 and IEC 62258-2. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. F
21、or undated references, the latest edition of the referenced document (including any amendments) applies. IEC 62258-1, Semiconductor die products Part 1: Requirements for procurement and use IEC 62258-2, Semiconductor die products Part 2: Exchange data formats 3 Terms and definitions For the purposes
22、 of this document, the terms, definitions and acronyms as given in IEC 62258-1 apply. 4 General To comply with IEC 62258-1, suppliers of die devices shall furnish information, which is necessary and sufficient for users of the devices at all stages of design, procurement, manufacture and test of pro
23、ducts containing them Whilst it is expected that much of the information supplied will be in the public domain and available from such sources as manufacturers data sheets, this standard does not place an obligation on a supplier to make information public. Any information that a supplier considers
24、to be proprietary or commercially sensitive may be supplied under the terms of a non-disclosure agreement. EN 62258-5:2006 6 Requirements and recommendations provided in this standard apply to electrical simulation models used to perform the following simulations: analysis of the signal propagation
25、within the electronic system; verification of the correct functionality of the electronic system; verification of the timing requirements; verification of the testability. Supporting information on the use of electrical simulation models is provided in Annex A. 5 Requirements for information on elec
26、trical simulation models 5.1 Information on the electrical simulation model 5.1.1 General Where a simulation model is provided, the information as defined in the following subclauses shall be given. 5.1.2 Model file name The name of the file containing the model shall be given. 5.1.3 Creation date T
27、he date on which the model file was created shall be given. 5.1.4 Model description A description of the model shall be provided in sufficient detail for a user to understand its scope and apply the corresponding simulator correctly. 5.1.5 Model source The source and originator of the model shall be
28、 stated. 5.1.6 Simulation program The name(s) of the simulation program(s) that will accept the model file as valid input shall be given. 5.1.7 Program version The version(s) of the simulation program(s) that are compatible with the given file shall be given. 5.1.8 Compliance level The level(s) of t
29、he simulation program(s) with which the model file complies shall be given (for example SPICE level 3). 5.1.9 Model scope The scope of the model shall be given, including any limitations in its use (for example VHDL behavioural model). 7 EN 62258-5:2006 5.2 Information on device connectivity 5.2.1 G
30、eneral The appropriate information, as data and/or model(s), describing the components connectivity features or characteristics should be stated. NOTE Examples of simulation models include IBIS (ANSI/EIA-656), SPICE, IMIC (JEITA ED-5302) and Touchstone. The following parameters are important for bar
31、e die and low frequency devices where terminal-to-terminal interference can be disregarded. 5.2.2 Pad capacitance The capacitance of the input, output, power and ground pads of the device should be stated. The node to which the capacitance is measured should also be stated. 5.2.3 Input buffer The el
32、ectrical model(s) of the input buffer(s) should be stated. The type and compliance level of the model(s) should also be stated. 5.2.4 Output buffer The electrical model(s) of the output buffer(s) should be stated. The type and compliance level of the model(s) should also be stated, as required in 5.
33、1. 5.2.5 ESD protection A description of the ESD protection circuitry, if any, should be given. If an ESD model is provided, the type and compliance level of the model shall also be stated, as required in 5.1. 5.3 Information on the timing simulation model The appropriate model(s) describing the com
34、ponents behaviour in the time dimension should be provided. Where required by the simulator the model of the device should be provided as an electronic file, so that it can be directly used as input to the simulation program. This is primarily intended for digital devices. NOTE Examples of timing si
35、mulation models include VITAL, VERILOG, IEEE 1029.1 Waveform and Vector Exchange Specification and IEC 61691-3-4, Timing expression in VHDL (in preparation). 5.4 Information on connection redistribution 5.4.1 General Where the electrical connection points or terminals of the device have been modifie
36、d or altered by use of one or more redistribution layers, information concerning the electrical parameters of any redistribution traces should be given. Information on multi-pin connections should be given in matrix form. 5.4.2 Redistribution trace resistance The resistance of the redistribution tra
37、ces, if any, with respect to the initial or original contact should be stated. Any assumed or known tolerances should also be stated. EN 62258-5:2006 8 5.4.3 Redistribution trace capacitance The self and mutual capacitance of the redistribution traces, if any, should be stated, preferably in matrix
38、form. Any assumed or known tolerances should also be stated. 5.4.4 Redistribution trace inductance The self and mutual inductance of the redistribution traces, if any, should be stated, preferably in matrix form. Any assumed or known tolerances should also be stated. 5.5 Information on package termi
39、nals 5.5.1 General Where the electrical connection points or terminals of the device have been modified by use of an alternate connection method, such as the addition of bumps, balls or bond-wires, information concerning the electrical parameters of any package terminals should be given. Information
40、 on multi-pin connections is to be given in matrix form. One suggested format for the matrix could be in CLGR (capacitance-inductance-conductance-resistance) format. 5.5.2 Terminal resistance The resistance of the package terminal (wire, bump, lead or ball) with respect to the original terminal shou
41、ld be stated. Any assumed or known tolerances should also be stated. 5.5.3 Terminal capacitance The self and mutual capacitance of the package terminal (wire, bump, lead or ball) should be stated, preferably in matrix form. Any assumed or known tolerances should also be stated. 5.5.4 Terminal induct
42、ance The self and mutual inductance of the package terminal (wire, bump, lead or ball) should be stated, preferably in matrix form. Any assumed or known tolerances should also be stated. 9 EN 62258-5:2006 Annex A (informative) Supporting information A.1 General For the purposes of this standard, an
43、electronic system is regarded as being composed of a number of processing elements (active components) that apply non-linear transformations to the electrical signals, connected to each other and to other electronic systems by means of an interconnection network that ideally leaves the electrical si
44、gnals unaltered (interconnections on the substrate) or applies linear transformations to them (passive components) and consisting of ICs and discrete components assembled on an interconnection substrate or board. The simulation of the electrical behaviour and verification of the correct functionalit
45、y of an electronic system are performed at the following levels: analysis of the signal propagation; verification of the correct functionality; verification of the timing requirements; verification of the testability. The simulation of an electronic system aims to check whether its electrical design
46、 performs the desired linear and non-linear transformations according to the specifications. The linear transformations are checked by the analysis of the signal propagation. The non-linear transformations are verified by the verification of the correct functionality and timing requirements. The abo
47、ve applies to digital, analogue and RF electronic systems. A.2 Analysis of the signal propagation In order to perform a proper analysis of the signal propagation of an electronic system, an interconnection block is defined as consisting of the output buffer of the active component that generates the
48、 signal (transmitting component); the interconnection network; the input buffer of the active component receiving the signal (receiving component). For this reason the models of the input and output buffers of a device are required. A.3 Verification of the correct functionality For analogue and RF s
49、ystems, this part corresponds to the analysis of the signal propagation. For digital systems, this part implies the comparison of sequences of logical states against given specifications, including compliance to the time frame. As far as the verification of the functionality of an electronic system is concerned, there are no additional requirements for systems using bare die, or minimally packaged components, with respect to systems using packaged components. EN 62258-5:2006 10 A.4 Ver
