1、 ENGINEERING MATERIAL SPECIFICATION Material Name Specification Number Date Action Changes 2014 06 11 N Status No replacement named L. Sinclair, NA 1996 10 23 Activated R. Gordon WP 3948-a Page 1 of 14 PRINTED CIRCUIT BOARDS, DOUBLE SIDED WSF-M22P3-A1 NOT TO BE USED FOR NEW DESIGN 1. SCOPE This spec
2、ification defines the performance requirements for rigid double sided circuit boards (DSBs). A double sided circuit board is defined as a circuit board with two or more layers interconnected electrically with copper plated vias. 2. APPLICATION This specification was released originally as the perfor
3、mance requirements for double sided circuit boards to be used as the interconnect for electronic modules. 3. REQUIREMENTS 3.1 QUALITY SYSTEM REQUIREMENTS Material suppliers and part producers must conform to Quality System Requirements, QS-9000. Material specification requirements are to be used for
4、 initial qualification of materials. A Control Plan for ongoing production verification is required. This plan must be reviewed and approved by the relevant Ford Materials activity and/or Ford Supplier Technical Assistance (STA) prior to production parts submission. Appropriate statistical tools mus
5、t be used to analyze process/product data and assure consistent processing of the materials. Part producers using this material in their products, must use Ford approved materials and must conform to a process control plan which has been approved by STA and/or the relevant Materials Activity. 3.2 IN
6、FRARED SPECTROPHOTOMETRY AND/OR THERMAL ANALYSIS Ford Motor Company, at its option, may conduct infrared and/or thermal analysis of material/parts supplied to this specification. The IR spectra and thermograms established for initial approval shall constitute the reference standard and shall be kept
7、 on file at the designated material laboratory. All samples shall produce IR spectra and thermograms that correspond to the reference standard when tested under the same conditions. ENGINEERING MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 2 of 14 3.3 CONDITIONING AND TEST CONDITIONS All test v
8、alues indicated herein are based on material conditioned in a controlled atmosphere of 23 +/- 2 C and 50 +/- 5 % relative humidity for not less than 24 h prior to testing and tested under the same conditions unless otherwise specified. 3.4 APPEARANCE Visually inspect the double sided circuit board u
9、nder a minimum magnification of 1.75X for the following criteria. 3.4.1 Circuit Traces 3.4.1.1 Conductor Width Reduction from Design, max . Conductors greater or equal to 0.300 mm 20 % . Conductors less than 0.300 mm 0.075 mm 3.4.1.2 Cracks or Voids are not permitted. Thickness reductions are allowa
10、ble provided they meet the minimum copper thickness requirements as designated on the engineering drawing. 3.4.1.3 Repair of broken traces is not permitted. 3.4.1.4 Rework of shorts between traces is permitted provided that reworked circuit meets the requirements in para 3.4.1.1. 3.4.2 Spacing Width
11、 The minimum width between noncommon conductors is 0.150 mm. Small specks or stray, nonelectrically connected, copper or other metallization are permitted provided that the specks are covered with soldermask that extends a minimum of 0.050 mm beyond the edge of each speck and a minimum of 0.100 mm s
12、pacing exists to any circuit trace. 3.4.3 Laminate (IPC-A-600, Laminate Defect Guidelines) Appearance irregularities such as measling, crazing and weave exposure of the base laminate are allowable if they meet IPC-A-600, Class III requirements. Foreign material is allowable if it is at least 0.25 mm
13、 from a conductor. ENGINEERING MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 3 of 14 3.4.4 Soldermask (IPC-SM-840, Class 3) . Cracked, peeled or delaminated soldermask is not permissible. . Missing soldermask is allowable provided that all conductors designed to be coated with soldermask are co
14、ated with soldermask and the soldermask extends a minimum of 0.050 mm into the adjacent space. . Voids are allowable provided that voids will not allow entrapment of flux. . Soldermask on solder pads is not allowable unless specified by the design. . Soldermask skips shall be acceptable provided tha
15、t all conductors designed to be coated with soldermask are coated with soldermask and the soldermask extends a minimum of 0.050 mm into the space between two traces on at least one side of the space. 3.4.5 Component Diagram (Legend Silkscreen) . The component diagram must be legible from a distance
16、of 25 cm to an observer with vision corrected to 20/20. . The component diagram ink is not permitted on solderable surfaces. 3.4.6 General 3.4.6.1 PTH Requirements Metallic nodules or other obstructions within a plated through hole are allowable provided that the internal diameter meets the minimum
17、diameter as defined by the applicable drawing. Missing holes are not permitted. 3.4.6.2 NPTH Requirements Metallic nodules, plating, legend silkscreen ink, soldermask or other obstructions are not permitted in holes designated as non-plated through holes. Missing holes are not permitted. ENGINEERING
18、 MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 4 of 14 3.4.6.3 Plugged Plated Through Holes All PTHs designated to be filled with plugging material shall be filled per the print. If not designated on the print, the minimum fill shall be a thickness which prevents gas from passing through the PT
19、H. A halo of solder is permissible around the hole circumference on side in which the hole was not plugged from. A continuous slug or film of solder over the entire plugged PTH is not permitted. 3.5 DIMENSIONAL 3.5.1 Hole Size 3.5.1.1 Plated Through Holes (PTH) The diameter of one of each PTH hole s
20、ize on each board on a panel shall be measured using pin gages or an alternative measuring instrument approved by Materials Engineering. 3.5.1.2 Non-plated Through Holes (NPTH) The diameter of each NPTH hole size on each board on a panel shall be measured using pin gages or an alternative measuring
21、instrument approved by Materials Engineering. 3.5.2 Hole Location Measure the X and Y coordinates of 4 holes, one selected from each of the outer corners from each board on a panel. Hole locations shall be determined using an optical comparator. All measurements are to be determined to four decimal
22、places with three place accuracy and be based on the datums defined on the applicable drawing. 3.5.3 External Registration Visually inspect the DSB under a minimum magnification of 1.75X. 3.5.3.1 Copper Conductor to Hole Location 3.5.3.1.1 PTHs Accepting Leaded Components The minimum annular ring as
23、 a function of the nominal annular ring is defined in the table below. The minimum annular ring shall not be less than 0.050 mm regardless of the nominal annular ring dimension. ENGINEERING MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 5 of 14 Nominal Annular Ring Minimum Annular Ring (mm) (mm)
24、 0.300 0.150 3.5.3.1.2 PTHs Not Accepting Leaded Components (Vias) The minimum annular ring is 0.050 mm. 3.5.3.2 Soldermask to Copper Conductor Measure the true position location of the soldermask pattern relative to the copper conductor pattern using an optical comparator. All measurements must be
25、determined to four decimal places with three place accuracy. The maximum misregistration requirements for a screen printed and photoimageable soldermask are listed below. Soldermask Type (Diametrical True Position) Screen Printed 0.280 mm Photoimaged 0.100 mm 3.5.3.3 Component Diagram (Legend Silksc
26、reen) to Copper Conductor Measure the true position location of the component diagram pattern relative to the copper conductor pattern using an optical comparator conductor. All measurements must be determined to four decimal places with three place accuracy. Diametrical True Position, max 0.280 mm
27、3.5.4 Bow and Twist (IPC-TM-650, Method 2.4.22) 3.6 CONSTRUCTION 3.6.1 Surface Copper The thickness of each copper layer shall be measured using a microsection per IPC-TM-650, Method 2.1.1. 3.6.2 Plated Through Hole Wall Thickness The plated through hole copper wall thickness shall be measured using
28、 a microsection per IPC-TM-650, Method 2.1.1. The average copper wall thickness must be greater than 0.025 mm. Localized reductions which do not reduce the copper hole wall thickness below 0.020 and do not reduce the average copper wall thickness below 0.025 mm are permissible. 3.6.3 Protective Coat
29、ing ENGINEERING MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 6 of 14 The thickness of the protective coating, if applicable, covering unmasked copper areas shall be checked at three different locations on each DSB for each manufacturing panel using microsectioning techniques per IPC-TM-650, Me
30、thod 2.1.1, X-ray fluorescence or an alternative method approved by Materials Engineering. An average of 4 measurements from the center of each quadrant of a representative SMD (surface mount device) pad shall be reported. The thickness measurements shall be taken such that the outer 0.025 mm wide p
31、eriphery of each pad is excluded. Organic antioxidant treatments such as benzotriazole are exempt from this requirement. 3.6.4 Dielectric Thickness The thickness of the dielectric between each layer and the total thickness shall be measured using a microsection per IPC-TM-650, Method 2.1.1. The numb
32、er of plies of glass, if applicable, shall be counted to insure compliance with the specific DSB print. 3.6.5 Hole Plugging Percent Fill When specified on the print, the percent fill of the hole plugging material shall be measured using a microsection per IPC-TM-650, Method 2.1.1 or an alternative m
33、ethod approved by Materials Engineering. The percent fill shall be defined as the thickness of the hole plugging material from the fill side to the bottom of the meniscus on the opposite side divided by the length of the copper barrel multiplied by 100 % (See Figure 2). Voids in the plugging materia
34、l are acceptable as long as they are not interconnected. Hole Plug ThicknessCopper Barrel LengthPlugging MaterialFigure 2: Dielectric Plugged PTH/Via 3.7 ELECTRICAL ENGINEERING MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 7 of 14 All DSBs shall be tested for electrical continuity and isolation
35、 per the requirements of the particular design. 3.7.1 Electrical Continuity The resistance between any two common conductors shall have a resistance of less than 10 ohms. 3.7.2 Electrical Isolation The resistance between any two non-common conductors shall be at least 10 megaohms when tested with a
36、voltage between 100 to 300 volts. 3.8 GENERAL 3.8.1 Cleanliness, max 1.5 ug NaCl/sq cm (IPC-TM-650, Method 2.3.26) The ionic cleanliness shall be measured before and after the application of soldermask using an Ionograph or method approved by Materials Engineering. Table 1 provides the maximum ionic
37、 cleanliness levels for common alternative ionic cleanliness measurement techniques. Table 1 - Ionic Cleanliness Contamination Levels Method ug NaCl/cm2 Omega Meter 1.05 Ion Chaser 2.40 3.8.2 Solderability (WSF-M22P1-A1) Class will be defined on the specific DSB print. If no class is specified, clas
38、s 1 is assumed. 3.8.3 Plated Through Hole Integrity 3.8.3.1 As Manufactured (Prior to Thermal Stress) Microsection PTHs per paragraph 3.5.4 and evaluate under a minimum of 100X magnification for the following requirements: . Plating voids are not allowed. . Burrs, nodules and glass fiber protrusions
39、 are allowed provided the minimum hole diameter is met. . Laminate voids greater than 0.075 mm in dimension are not allowed. . Lifted external pads are not allowed. ENGINEERING MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 8 of 14 3.8.3.2 After Thermal Stress (Solder Float) Thermally stress a P
40、TH coupon removed from a production representative circuit board per IPC-TM-650, method 2.6.8 with the following exceptions: . 4 h conditioning at standard conditions prior to thermal stress. (See para 3.3.) . Test coupons shall not be baked prior to testing. . Solder bath temperature shall be 235 C
41、. After thermal stress exposure, microsection PTHs per IPC-TM-650, Method 2.1.1 and evaluate under a minimum of 100X magnification for the following requirements: . Plating voids are not allowed. . Separation of plating is not permitted. . Cracks in the PTH hole wall or external copper pads are not
42、permitted. . Laminate voids greater than 0.075 mm in dimension are not permitted. . Lifted external pads are allowed provided that 50 % of the pad annular ring width remains bonded to the base laminate. . Resin recession or hole wall pullaway is permitted provided the resin recession is no greater t
43、han 0.075 mm as measured from the plated through hole copper and the resin recession does not extend more than 5 percent of the cumulative hole wall length. 3.9 DURABILITY 3.9.1 Resistance to Solvents, weight 2 % gain, max (IPC-TM-650, method 2.3.3) No damage or degradation of the conductor pattern
44、(legend silkscreen), soldermask or base laminate is permitted when exposed to the following solvents: Isopropyl Alcohol Acetone 1 % Adipic Acid Solution in water 2 % Adipic Acid Solution in Isopropyl Alcohol Koki Flux ENGINEERING MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 9 of 14 3.9.2 Moist
45、ure and Insulation 5 x 10E08 Ohms Resistance, min (IPC-TM-650, Method 2.6.3.1A) A set of non-common parallel circuit traces which run parallel for a minimum of 25 mm and are separated by a specific designs minimum line spacing shall be tested. 3.9.3 Thermal Cycle Thermal cycle DSBs per the following
46、 temperature extremes listed in Table 2. The class for each circuit board shall be listed on the print. If no class is identified, class 3 is assumed. Successful qualification to a more severe thermal cycle requirement provides qualification to a less severe requirement. The thermal cycle profile is
47、 shown in Figure 1. The profile consists of 25 minutes at each temperature extreme with a minimum transition time of 5 minutes. The DSBs must meet the Appearance (para 3.7) requirements prior to thermal cycling and be representative of DSB that can meet all aspects of this specification. After therm
48、al cycling, the tested DSBs must meet the Appearance (para 3.4) and Electrical (para 3.7) requirements. Additionally, a microsection of the smallest diameter PTH shall be taken from at least 3 randomly chosen DSBs. The microsections must meet the PTH requirements listed in para 3.8.3.2. Table 2: The
49、rmal Cycle Requirements based on Application Severity Class 1 Class 2 Class 3 Application Severity Mild Moderate Severe Thermal Cycle Range -40 to 85 C -40 to 105 C -40 to 125 C Number or Cycles 500 1000 1000 ENGINEERING MATERIAL SPECIFICATION WSF-M22P3-A1 WP 3948-b Page 10 of 14 Figure 1: Thermal Cycle Profile 3.10 ADDITIONAL REQUIREMENTS Specific requirements for material and/or manufactured parts shall be specified on the Engineering drawing, Engineering parts specification and/or performance specificatio
