1、 JEDEC STANDARD Universal Flash Storage Host Controller Interface (UFSHCI) Version 2.1 JESD223C (Revision of JESD223B, September 2013) MARCH 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through t
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9、ate Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 223C -i- UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), Version 2.1 Contents Page 1 Scope . 1 2 Normat
10、ive Reference . 1 3 Acronyms, Terms and Definitions, Keywords, and Conventions 2 4 Architectural Overview . 5 4.1 Outside of Scope 5 4.2 Interface Architecture 6 4.2 Interface Architecture (contd) 7 4.3 Transfer Request Interface . 8 4.3 Transfer Request Interface (contd) . 9 4.4 Limitations . 9 5 U
11、FS Host Controller Register Interface 9 5.1 Register Map 10 5.2 Host Controller Capabilities Registers . 11 5.2.1 Offset 00h: CAP Controller Capabilities 11 5.2 Host Controller Capabilities Registers (contd) . 12 5.2.2 Offset 08h: VER UFS Version . 12 5.2.3 Offset 10h: HCPID Host Controller Identifi
12、cation Descriptor Product ID 12 5.2.4 Offset 14h: HCMID Host Controller Identification Descriptor Manufacturer ID . 12 5.2.5 Offset 18h: AHIT Auto-Hibernate Idle Timer 13 5.3 Operation and Runtime Registers 14 5.3.1 Offset 20h: IS Interrupt Status 14 5.3.2 Offset 24h: IE Interrupt Enable . 16 5.3.3
13、Offset 30h: HCS Host Controller Status . 17 5.3.4 Offset 34h: HCE Host Controller Enable . 18 5.3.5 Offset 38h: UECPA Host UIC Error Code PHY Adapter Layer 18 5.3.6 Offset 3Ch: UECDL Host UIC Error Code Data Link Layer . 19 5.3.7 Offset 40h: UECN Host UIC Error Code Network Layer 19 5.3.8 Offset 44h
14、: UECT Host UIC Error Code Transport Layer . 20 5.3.9 Offset 48h: UECDME Host UIC Error Code . 20 5.3.10 Offset 4Ch: UTRIACR UTP Transfer Request Interrupt Aggregation Control Register . 21 5.4 UTP Transfer Request Registers 22 5.4.1 Offset 50h: UTRLBA UTP Transfer Request List Base Address . 22 5.4
15、.2 Offset 54h: UTRLBAU UTP Transfer Request List Base Address Upper 32-bits . 22 5.4.3 Offset 58h: UTRLDBR UTP Transfer Request List Door Bell Register 23 5.4.4 Offset 5Ch: UTRLCLR UTP Transfer Request List CLear Register . 23 5.4.5 Offset 60h: UTRLRSR UTP Transfer Request List Run Stop Register . 2
16、3 5.4.6 Offset 64h: UTRLCNR UTP Transfer Request List Completion Notification Register 24 5.5 UTP Task Management Registers . 25 5.5.1 Offset 70h: UTMRLBA UTP Task Management Request List Base Address . 25 5.5.2 Offset 74h: UTMRLBAU UTP Task Management Request List Base Address Upper 32-bits . 25 5.
17、5.3 Offset 78h: UTMRLDBR UTP Task Management Request List Door Bell Register 25 5.5.4 Offset 7Ch: UTMRLCLR UTP Task Management Request List CLear Register 26 5.5.5 Offset 80h: UTMRLRSR UTP Task Management Request List Run Stop Register 26 JEDEC Standard No. 223B -ii- Contents (contd) Page 5.6 UIC Co
18、mmand Registers . 27 5.6.1 Offset 90h: UICCMD UIC Command 27 5.6.2 Offset 94h: UICCMDARG1 UIC Command Argument 1 . 28 5.6.3 Offset 98h: UICCMDARG2 UIC Command Argument 2 . 29 5.6.4 Offset 9Ch: UICCMDARG3 UIC Command Argument 3 . 30 5.6.5 Attributes for Local L2 Timers 30 5.7 Vendor Specific Register
19、s 31 5.7.1 Offset C0h to FFh: VS Vendor Specific . 31 5.8 Crypto Registers 32 5.8.1 Offset 100h: CCAP Crypto Capability . 32 5.8.2 x-CRYPTOCAP Crypto Capability X 33 5.8.3 x-CRYPTOCFG Crypto Configuration X 34 6 Data structures . 36 6.1 UTP Transfer Request List 36 6.1.1 UTP Transfer Request Descrip
20、tor 36 6.1.2 UTP Command Descriptor 40 6.2 UTP Task Management Request List 42 6.2.1 UTP Task Management Request Descriptor 42 6.3 Key Organization for Cryptographic Algorithms 44 6.3.1 AES-XTS . 44 6.3.2 Bitlocker-AES-CBC 46 6.3.3 AES-ECB . 47 6.3.4 ESSIV-AES-CBC 48 7 Theory of Operation 48 7.1 Hos
21、t Controller Configuration and Control . 49 7.1.1 Host Controller Initialization . 49 7.1.2 Configuration and control 51 7.1.3 CRYPTOCFG Configuration Procedure . 51 7.2 Data Transfer Operation 52 7.2.1 Basic Steps when Building a UTP Transfer Request . 53 7.2.2 UPIU Processing 54 7.2.3 Processing U
22、TP Transfer Request Completion . 56 7.3 Task Management Function . 58 7.3.1 Basic Steps when Building a UTP Task Management Request . 58 7.3.2 Processing UTP Task Management Completion . 58 7.4 UIC Power Mode Change 59 7.5 UFSHCI Internal Rules 61 7.5.1 Command Processing Order 61 7.5.2 RTT Processi
23、ng Rules 62 7.5.3 Data Unit Processing Order for Cryptographic operations 62 8 Error reporting and handling . 63 8.1 Error Types 63 8.1.1 System Bus Error . 63 8.1.2 UIC Error . 63 JEDEC Standard No. 223A -iii- Contents (contd) Page 8.1.3 UIC Command Error 63 8.1.4 UTP Error 64 8.1.5 Host controller
24、 Fatal Error . 64 8.1.6 Device Error . 64 8.1.7 Hibernate Enter/Exit Error . 65 8.2 Error Handling . 65 8.2.1 System Bus Error Handling . 65 8.2.2 UIC Error Handling . 66 8.2.3 UIC Command Error Handling 66 8.2.4 UTP Error Handling . 67 8.2.5 Host Controller Error Handling . 67 8.2.6 Device Error Ha
25、ndling . 67 8.2.7 Hibernate Enter/Exit Error Handling . 67 9 Encryption ENGINE DETAILS (Informative) . 68 9.1 AES-XTS . 68 9.1.1 Overview 68 9.1.2 Data Unit Size 68 9.1.3 Tweak 69 9.2 Bitlocker AES-CBC . 69 9.2.1 Background 69 9.2.2 Overview 70 9.2.3 Sector (Data Unit) Size S . 70 9.2.4 Sector Offse
26、t O 70 9.2.5 Sector Initialization Vector (IV) 71 9.2.6 Encryption / Decryption . 71 9.3 AES-ECB . 71 9.3.1 Overview 71 9.4 ESSIV-AES-CBC 72 9.4.1 Background 72 9.4.2 Data Unit Size 72 9.4.3 Sector Number (SN) 72 9.4.4 Initialization Vector (IV) . 72 9.4.5 Encryption / Decryption . 72 JEDEC Standard
27、 No. 223B -iv- Contents (contd) Page Figures Figure 1 UFS Architecture Overview 5 Figure 2 General architecture of UFS Host Controller Interface. 6 Figure 3 A conceptual block diagram of UFS host system 8 Figure 4 x-CRYPTOCFG Array Entry Layout 35 Figure 5 UTP Transfer Request Descriptor . 36 Figure
28、 6 UTP Command Descriptor (UCD) 40 Figure 7 Data structure for Physical Region Description Table 41 Figure 8 UTP Task Management Request Descriptor. 42 Figure 9 AES128-XTS Key Layout . 44 Figure 10 AES192-XTS Key Layout . 45 Figure 11 AES256-XTS Key Layout . 45 Figure 12 AES128-CBC Key Layout 46 Fig
29、ure 13 AES256-CBC Key Layout 46 Figure 14 AES128-ECB Key Layout . 47 Figure 15 AES256-ECB Key Layout . 47 Figure 16 Host controller link startup sequence 50 Figure 17 UIC Power mode change . 60 Figure 18 Command processing order . 61 Figure 19 Byte Order For Data Unit Processing in Cryptographic ope
30、rations 62 Figure 20 AES-XTS Encryption 68 Figure 21 Bitlocker AES-CBC Encryption 70 Figure 22 IV Derivation from Sector Offset 71 Figure 23 AES-ECB Encryption 71 Figure 24 ESSIV-AES-CBC Encryption . 72 Tables Table 1 Outbound UPIUs generated by software .54 Table 2 Outbound UPIU generated by UTP En
31、gine 54 Table 3 Inbound UPIUs consumed by software .55 Table 4 Inbound Data In UPIU handled by UTP Engine .55 Table 5 Inbound RTT UPIU handled by UTP Engine .56 JEDEC Standard No. 223B Page 1 UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI) (From JEDEC Board ballot JCB-16-14, formulated un
32、der the cognizance of the JC-64.1 Subcommittee on Electrical Specifications and Command Protocols (Item 204.02).) 1 Scope This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform inter
33、face method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and
34、the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to UFS, Universal Flash Storage (UFS). The reader is assumed to be familiar with UFS, MIPI-UNIPRO, and MIPI-M-PHY. Clause 4 provides a brief overview of
35、 the architectural overview of UFS. Clause 5 describes the register interface of UFSHCI. Clause 6 describes the data structure used by UFSHCI. Clause 7 provides a theory of operation for UFSHCI. Clause 8 describes the error recovery process for UFSHCI. 2 Normative Reference The following normative d
36、ocuments contain provisions that, through reference in this text, constitute provisions of this standard. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on this standard are encouraged to investigate the p
37、ossibility of applying the most recent editions of the normative documents indicated. For undated references, the latest edition of the normative document referred to applies. MIPI-M-PHY, MIPI Alliance Specification for M-PHYSM, Version 3.00.00 MIPI-UniPro, MIPI Alliance Specification for Unified Pr
38、otocol (UniProSM), Version 1.6.00 MIPI-DDB, MIPI Alliance Specification for Device Descriptor Block (DDB), Version SAM, INCITS T10 draft standard: SCSI Architecture Model 5 (SAM5), Revision 05, 19 May 2010 SPC, INCITS T10 draft standard: SCSI Primary Commands 4 (SPC-4), Revision 27, 11 October 2010
39、SBC, INCITS T10 draft standard: SCSI Block Commands 3 (SBC3), Revision 24, 05 August 2010 UFS, JEDEC JESD220C, Universal Flash Storage (UFS 2.1) JEP, JEDEC JEP106, Standard Manufacturers Identification Code JEDEC Standard No. 223B Page 2 3 Acronyms, Terms and Definitions, Keywords, and Conventions 3
40、.1 Acronyms DID Device ID GB Gigabyte HCI Host Controller Interface KB Kilobyte LUN Logical Unit Number MIPI Mobile Industry Processor Interface MB Megabyte NA Not applicable PRDT Physical Region Description Table UCD UTP Command Descriptor UFS Universal Flash Storage UPIU UFS Protocol Information U
41、nit UTP UFS Transport Protocol UTMRD UTP Task Management Request Descriptor UTRD UTP Transfer Request Descriptor 3.2 Terms and Definitions Byte: An 8-bit data value with most significant bit labeled as bit 7 and least significant bit as bit 0. Device ID: The bus address of a UFS device. Doubleword:
42、A 32-bit data value with most significant bit labeled as bit 31 and least significant bit as bit 0. Dword: A 32-bit data value, a Doubleword. Gigabyte(GB): 1,073,741,824 or 230 bytes. Host: An addressable device on the UFS bus which is usually the main CPU that hosts the UFS bus. Kilobyte(KB): 1024
43、or 210bytes. Logical Unit Number: A numeric value that identifies a logical unit within a device. Megabyte(MB): 1,048,576 or 220 bytes. Quadword: A 64-bit data value with most significant bit labeled as bit 63 and least significant bit as 0. JEDEC Standard No. 223B Page 3 3.2 Terms and Definitions (
44、contd) UFS Protocol Information Unit: Information transfer (communication) between a UFS host and device is done through messages which are called UFS Protocol Information Units. NOTE The messages are UFS defined data structures that contain a number of sequentially addressed bytes arranged as vario
45、us information fields. UTP Transfer Request Descriptor: A data structure in system memory that contains a UTP command and additional contextual information needed to carry out the command operation. NOTE The command is limited to UFS adopted INCITS T10 draft standard command sets (see UFS), UFS nati
46、ve command set and Device Management function that uses UTP protocol. A UTP Transfer Request Descriptor is built by the host and is targeted at the attached UFS device. UTP Task Management Request Descriptor: A data structure in system memory that contains a UTP Task Management Function and the addi
47、tional contextual information needed to execute the function. NOTE A UTP Transfer Request Descriptor is built by the host and is executed by the attached UFS device. Unit: A bus device. Word: A 16-bit data value with most significant bit labeled as bit 15 and least significant bit as bit 0. zero-bas
48、ed value: A numeric value N (N 0) represented by N-1 3.3 Keywords Several keywords are used to differentiate levels of requirements and options, as follow: Expected A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard. Other hardware and s
49、oftware design models may also be implemented. Ignored A keyword that describes bits, bytes, quad lets, or fields whose values are not checked by the recipient. Mandatory A keyword that indicates items required to be implemented as defined by this standard. May A keyword that indicates flexibility of choice with no implied preference. Optional A keyword that describes features which are not required to be implemented by t
