1、JEDEC STANDARD Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilities JESD241 DECEMBER 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors l
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9、03 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 241 -i- PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE INSTABILITIES CONTENTS 1 Scope . 1 2 Normative references . 1 3 Terms
10、and definitions . 2 4 Technical requirements . 4 4.1 Constant current threshold Voltage VT(ci)determination4 4.2 Characterization of linear mode VT(ci) BTI VTshifts 6 5 BTI Stress/test procedure 6 5.1 Description of adopted VGS/VDS stress/test waveforms . 6 5.2 Selection of Device under test (DUT) 8
11、 5.3 Initial (before stress) VT(ci)estimation at time t0(typically 0 s). . 8 5.4 Stress/test Cycle . 8 5.5 Evaluation of tfit, tf, for a given . 10 5.6 IV characterization after tf12 6 DC BTI fast switching technical requirements . 12 6.1 Wafer level equipment requirements . 12 6.2 Test structure re
12、quirements 12 6.3 Measurement requirements 12 6.4 Hardware sampling requirements 13 7 DC BTI End of Life (EOL) estimation for a wide device . 13 8 Required reporting 14 Annex A (informative) Recommendations to estimate alternate device parameters . 16 Annex B (informative) Selection of a wide device
13、 18 Annex C (informative) Experiment design to find wide device dc BTI model parameters . 21 JEDEC Standard No. 241 ii Foreword This test procedure was drafted and approved by JEDEC JC-14.2 Wafer-Level Reliability Committee consisting of recognized bias-temperature instability industry experts from
14、foundries and fabless member companies. The objective of this Bias Temperature Instability (BTI) stress/test procedure is to provide a minimum recommendation for a simple and consistent comparison of End of Life (EOL) mean threshold voltage (VT) shift due to BTI aging at agreed worst dc use conditio
15、ns. Both PTBI and NBTI are addressed in this characterization procedure and can be easily implemented to allow comparison of BTI on different mature CMOS processes. Bias-temperature instabilities are investigated in a capacitor-like configuration with the MOSFET gate biased (|VGS| 0) at high tempera
16、ture while other contacts are grounded (no channel conduction) (VDS = 0). Typically physical BTI damage results in the degradation of the voltage threshold (VT), as well as changes in the channel mobility and transconductance. As a consequence of the degradation of device parameters the circuit may
17、fail to fully meet functional requirements. The procedure enables only: Comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Estimate BTI aging of large area MOSFET transistor with a channel width, Wdes (Wdes Wmin see
18、Annex B) and length Ldes. Estimate of linear mean VTshift as a measure of device flatband shift dependence on BTI aging. Annex A. provides recommendations to estimate other device parameters associated to BTI induced mobility and transconductance degradation. BTI qualification and accept-reject crit
19、eria are not given in this document. Historical discrepancies resulting from inconsistent observation, metrology capabilities and quantification of BTI damage on the same CMOS process and technology are addressed by using this procedure as benchmark for BTI comparison. The stress/test BTI dc charact
20、erization methodology can be used within the limits of this procedure as a benchmark to monitor BTI damage as related to flatband VTshift. Future revisions this proposed methodology will be introduced as more experimental findings become available. JEDEC Standard No. 241 Page 1 PROCEDURE FOR WAFER-L
21、EVEL DC CHARACTERIZATION OF BIAS TEMPERATURE INSTABILITIES (From JEDEC Board Ballot JCB-15-22, formulated under the cognizance of the JC-14.2 Subcommittee on Wafer-Level Reliability.) 1 Scope The scope of this document is to provide a minimum common protocol for foundries and fabless customers to co
22、mpare the dc BTI induced mean VT shift at an agreed End of Life (EOL) of a MOSFET transistor with a channel width, Wdes (Wdes Wmin See Annex B) and length Ldesof a manufacturable CMOS process and technology. The BTI comparison is proposed at an assumed worst dc use conditions (VDDmax, TJmax). The pr
23、ocedure applies to both Negative (VGS 0) (PBTI) BTI conditions for both pMOSFET and nMOSFET transistors. The proposed procedure consists of two parts: 1) BTI stress/test characterization methodologyA two-step stress/test waveform with VGSand VDS switching between a capacitor-like BTI stress with no
24、channel conduction (VGS = VGSstr, VDS= VDSstr = 0) and a single drain current, ID, measurement in linear mode (VGS =VGStst, VDS = VDStst 0) with no channel conduction (VDS= 0). NOTE 2 Wearout results in an increase in the |V(TO)| with consequential decrease in drain current and possibly transconduct
25、ance. BTI aging with VGStfitwith the different VGSstrand Tstrstress conditions selected used to develop the BTI model (similar to the graphic representation for VGS1and VGS2in Figure 7). It is generally observed that a very large ( 1 s) and small ( 1 s) value of requires larger tfitto guarantee that
26、 a similar power law exponent, n, can be used to describe the VTshift vs. tstr dependence across the selected VGSstrand Tstrstress conditions. It is true that a VTshift power law dependence on ttst can be obtained at any . It is, however, important that is selected to yield a similar n at the differ
27、ent selected VGSstrand Tstrconditions. For a given , once tfitis defined, the time exponent, n, is obtained from a linear fit of the log(|VT(ci)|) vs. log(ttst) relation with ttstin the time range tf ttst tfitwith tf in the tf tfittime interval that extends between 2-3 decades in time. Any values of
28、 , tfitand tfthat are selected must be demonstrated with the accelerated VGSstrand Tstrstress conditions such that a similar interval time exponent, n, is estimated to characterize the dc BTI damage. Figure 8 Example of the impact of selection to tfitshowing that a large and small is correlated to a
29、 larger tfit which is required for a power law regression of the VTshift vs. tstrA minimum stress-to-test measuring delay of approximately 1 ms is typically needed from commercial wafer level probers to allow stable settling times from waveform (VGSstr/VDSstr) to (VGStst/VDStst). If 1 ms is adopted,
30、 a tfit 100 s is typically applicable for VGSstrrange between 1.2 VDDnomand 1.7 VDDnom. For a value of much less than 1 ms, extra care needs to be paid to select tfit consistently with its definition. For tf tstr tfit the typical BTI model parameters (i.e., , Ea, n) can be estimated. Annex C recomme
31、ndations on the design of experiment involving VGSstrand Tstrto extract the BTI model parameters. JEDEC Standard No. 241 Page 12 5.6 IV characterization after tfAfter stress, an optional IV measurement (Figure 4 (b) may be carried out to verify that a parallel IV shift occurs during stress which sub
32、stantiates that the BTI shift is caused by flat-band shift change. 6 DC BTI fast switching technical requirements 6.1 Wafer level equipment requirements The measurement system must be capable of the simultaneous application of voltage and measurement of current at the gate, drain, and substrate term
33、inals of the device. The system must be able to measure 100 nA with a 10% resolution. The voltage overshoot must not exceed 1% of the applied voltage. The measuring delay should be on the order of a few milliseconds. 6.2 Test structure requirements Only devices with large active area should be used
34、to reduce the intrinsic statistical variation due to random fluctuations in BTI induced by area scaling. Typically, a smaller channel area (Wdes x Ldes), will require a larger sample size to reach a reasonable statistical confidence level. Refer to Annex B for details. MOSFETs with different gate di
35、electric thickness, allowed by the technology, must be evaluated. The gate, drain and source terminals of the device must be contacted, i.e., they shall not be floating. The well terminal used during stress/test must be at the same bias conditions as in operation (typically VW= 0 if bulk). To minimi
36、ze parasitic voltage drops between the probe pads (VProbe) and the device terminals (Vdevice), the wiring resistances (RW) from the probe pads to the device gate, source, drain, and well are selected such that the voltage drop (IRW) is less than 1% Vdevice. To quantify the intrinsic BTI sensitivity,
37、 it is required to stress MOSFETs with MOL and BEOL levels designed with the nominal antenna rules allowed by the technology design. If a given BEOL level is protected by design rules then that gate protection must be used. 6.3 Measurement requirements The device should be measured at the wafer-leve
38、l on a stable probe station utilizing a vacuum chuck. The chuck or fixture temperature shall be set at the stress temperature during stress and test. Once set, the temperature must be maintained to within +/- 1.0 C of the set point for the duration of the test. At the end of each BTI stress interval
39、, the stress is terminated and device parameters are measured. The stress time interval and the testing delay should be known to an accuracy of +/- 1% for stress time intervals. JEDEC Standard No. 241 Page 13 6.4 Hardware sampling requirements A minimum of 3 lots with 2 wafers/lot representative of
40、the nominal process of record (POR) hardware should be used. Depending on the measured variability of the BTI shifts for a given device an adequate sample size is required to achieve an assumed statistical confidence level (90%). A minimum recommended, 4 chips per stress bias per temperature are use
41、d for large area MOSFET BTI characterization (see Annex B.). 7 DC BTI End of Life (EOL) estimation for a wide device The absolute value of mean VT(ci)(shift, ( nullnullnull(nullnull)null), dependence on VGSstrs and tstr is typically given by one of the following equations: nullnullnull(nullnull)null
42、=nullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull(5a) or nullnullnull(nullnull)null=Cnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull(5b) where: Toxhas the value measured in line Eais the temp
43、erature activation energy (eV) n is the stress time exponent. is the voltage acceleration exponent. In the tf tstr tfitrange a procedure on how to estimate the values of the model parameters C, n, Eaand is given in the Annex C. The coefficients C, n, Eaand of the dc BTI model are estimated for a wid
44、e device and are representative of the CMOS process under evaluation. A wide device is stressed to reduce the random fluctuation contributions to BTI aging. Annex B gives the recommended procedure to select and design a large active area device for BTI stressing. Typically a MOSFET with Ldes = Lnoma
45、nd Wdes 1 m can be used for BTI modeling. This procedure recommends a DC BTI mean VT(ci) shift estimate at a given End of Life (EOL) as a means to compare BTI sensitivity between CMOS processes or technologies. From eq. 4, once the BTI model parameters are estimated, the mean VT(ci) shift at an agre
46、ed dc EOL () for the worst case use conditions VDDnom(VDDmax) and channel temperature (TMAX) is given by: nullnullnull(nullnull)null=Cnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull(6a) or nullnullnull(nullnull)null=Cnullnullnullnullnullnullnullnullnullnullnu
47、llnullnullnullnullnullnullnullnullnullnullnull(6b) For an agreed dc lifetime a mean shift can be estimated. Comparison of different processes or technologies is done using the estimated VTshift. JEDEC Standard No. 241 Page 14 8 Required reporting To ensure consistency, the following information rele
48、vant to the MOSFET BTI measurement shall be reported. Table 2 Parameters to be reported Required information Description Test Transistor Identification Provide information sufficient to uniquely identify the MOSFET tested. Lot #, Wafer #, chip location in the wafer Device Wdes/LdesWdesused to estima
49、te process(Typically Wdes 1 m) for Ldes= Lnom. Technology/process features Key elements of the MOSFET device design such as gate dielectric process, source/drain engineering etc. VDDnomThe nominal power supply for the technology under investigation. TMAXThe maximum junction temperature specified at use conditions for the technology under consideration ToxTOXvalue entered in the BTI model (Toxgl, Tinv, etc.) and adopted for the oxide thickness of the selected de
