1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD250JULY 2017JEDECSTANDARDGRAPHICS DOUBLE DATA RATE(GDDR6) SGRAM STANDARD NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subsequently reviewed and approved
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3、imumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay involve patents or articles, materials, or processes. By su
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9、DEC Solid State Technology Association3103 North 10th Street, Suite 240SArlington, Virginia 22201or call (703) 907-7559JEDEC Standard No. 250-i-Contents1 SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10、. . . . . . . . . . . . . . . . . . . . . 12 GDDR6 SGRAM STANDARD OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.3 DEFINITION
12、 OF SIGNAL STATE TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.4 DEFINITION OF CLOCKING TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13、 . . . . . . . . . . . . . . . . . . 42.5 CLOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 INITIALIZATION . . . . . . . . . . . . . . .
14、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.1 POWER-UP SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15、 . . . . . . . . . . . . 83.2 INITIALIZATION WITH STABLE POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.3 VENDOR ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17、 . . . . 154.1 COMMAND and ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.2 COMMAND ADDRESS BUS INVERSION (CABI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.3 BANK GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 TRAINING .
19、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.1 INTERFACE TRAINING SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20、. . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.2 COMMAND ADDRESS TRAINING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.3 WCK2CK TRAINING . . . . . . . . . . . . . . . . . .
21、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.4 READ TRAINING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22、 . . . . . . . . . . . . . . . . . . . . . . . . . . . 325.5 WRITE TRAINING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 MODE REGISTERS . . . . . . . . . .
23、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.1 MODE REGISTER 0 (MR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24、 . . . . . . . . . . . . . . . 426.2 MODE REGISTER 1 (MR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446.3 MODE REGISTER 2 (MR2) . . . . . . . . . . . . . . . . . . . . .
25、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466.4 MODE REGISTER 3 (MR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26、. . . . . . . . . . . . . . . . 486.5 MODE REGISTER 4 (MR4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506.6 MODE REGISTER 5 (MR5). . . . . . . . . . . . . . . . . . . .
27、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526.7 MODE REGISTER 6 (MR6) accesses start at a selected location and consists of a total of sixteen data words. Accesses begin with the registration of an Activate c
28、ommand, which is then followed by a Read, Write (WOM) or masked Write (WDM, WSM) command.The row and bank address to be accessed is registered coincident with the Activate command. The address bits registered coincident with the Read, Write or masked Write command are used to select the bank and the
29、 starting column location for the burst access.This specification includes all features and functionality required for GDDR6 SGRAM devices. In many cases the GDDR6 specification describes the behavior of a single channel. JEDEC Standard No. 250Page 42.3 DEFINITION OF SIGNAL STATE TERMINOLOGYGDDR6 SG
30、RAM will be operated in both ODT Enable (terminated) and ODT Disable (unterminated) modes. For highest data rates it is recommended to operate in the ODT Enable mode. ODT Disable mode is designed to reduce power and may operate at reduced data rates. There exist situations where ODT Enable mode can
31、not be guaranteed for a short period of time, i.e., during power up.Following are four terminologies defined for the state of a device (GDDR6 SGRAM or controller) signal during operation. The state of the bus will be determined by the combination of the device signal connected to the bus in the syst
32、em. For example, in GDDR6 it is possible for the SGRAM pin to be tristated while the controller signal is HIGH or ODT. In both cases the bus would be HIGH if the ODT is enabled. For details on the devices signals and their function see Sections 9.1 and 9.2.Device pin signal level: HIGH: A device sig
33、nal is driving the Logic “1” state. LOW: A device signal is driving the Logic “0” state. Hi-Z: A device signal is tristate. ODT: A device signal terminates with ODT setting, which could be terminating or tristate depending on Mode Register setting.Bus signal level: HIGH: One device on bus is HIGH an
34、d all other devices on bus are either ODT or Hi-Z. The voltage level on the bus would be nominally VDDQ. LOW: One device on bus is Low and all other devices on bus are either ODT or Hi-Z. The voltage level on the bus would be nominally VOL(DC) if ODT was enabled, or VSSif Hi-Z. Hi-Z: All devices on
35、bus are Hi-Z. The voltage level on bus is undefined as the bus is floating. ODT: At least one device on bus is ODT and all others are Hi-Z. The voltage level on the bus would be nominally VDDQ.2.4 DEFINITION OF CLOCKING TERMINOLOGY Data refers to the signal being clocked (e.g. DQ by WCK and CA by CK
36、 Half rate: clock is running at half of the data rate (e.g. WCK 4GHz and DQ at 8Gbps, or CK 1GHz and CA at 2Gbps) Quarter rate: clock is running at a quarter of the data rate (e.g. WCK 2GHz and DQ at 8Gbps) Eighth rate: clock is running at one eighth of the data rate (e.g. WCK internal 1GHz and DQ a
37、t 8Gbps) DDR (Double Data Rate): complement to half rate, referring to data relative to clock QDR (Quad Data Rate): complement to quarter rate, referring to data relative to clock ODR (Octa Data Rate): complement to eighth rate, referring to data relative to clockJEDEC Standard No. 250Page 52.5 CLOC
38、KINGThe GDDR6 SGRAM supports two operating modes for WCK frequency which differ in the DQ/DBI_n pin to WCK clock frequency ratio. The GDDR6 SGRAM supports DDR and QDR operating modes for WCK frequency which differ in the DQ/DBI_n to WCK clock frequency ratio.Figure 1 illustrates the difference betwe
39、en a DDR WCK and a QDR WCK. Figure 60 illustrates a WRITE command with a DDR WCK clock while Figure 61 illustrates a WRITE command with a QDR WCK clock. Figure 74 illustrates a READ command with DDR WCK clocking and Figure 75 illustrates a READ command with QDR WCK clocking. Other figures in the spe
40、cification are shown only with the DDR WCK for simplicity unless otherwise noted. GDDR6 SGRAM also supports 2 granularities for the WCK data clock in the device. GDDR6 SGRAM devices can be designed with either a WCK/byte or a WCK/word. The ball-out has provisions for a WCK/byte but also supports WCK
41、/word with the unused WCK balls as NC; the host must turn the unused WCK off.The DRAM info bits for WCK Granularity, WCK Frequency and Internal WCK can be read by the host during the initialization process to determine the WCK architecture for the device and for devices that support multiple frequen
42、cies, MR2 OP11 allows for the mode to be set. For the frequencies for each mode see Table 68.In both WCK QDR and DDR modes the GDDR6 device operates from a differential clock CK_t and CK_c. Command and Address (CA) are registered at every rising and falling CK edge. For both WCK DDR and QDR ratio th
43、e GDDR6 device can support either a full data rate EDC or a half data rate EDC. See EDC section for more details.A rising CK (or WCK) edge is defined as the crossing of the positive edge of CK_t (or WCK_t) and the negative edge of CK_c (or WCK_c). A falling CK (or WCK) edge is defined as the crossin
44、g of the negative edge of CK_t (or WCK_t) and the positive edge of CK_c (or WCK_c).Table 1 Example Clock and Interface Signal Frequency RelationshipPIN DDR WCK QDR WCK UNITCK_t, CK_c 1.5 1.5 GHzCA 3.0 3.0 Gbps/pinWCK_t, WCK_c 6.0 3.0 GHzDQ, DBI_n 12.0 12.0 Gbps/pinEDC 6.0 12.0 6.0 12.0 Gbps/pinJEDEC
45、 Standard No. 250Page 6CK_tCK_cCADATA *1WCK_tWCK_cf (i.e. 1.75 GHz)2f (i.e. 3.5 Gbps)4f (i.e. 7.0 GHz)8f (i.e. 14.0 Gbps)CK_tCK_cCADATA *1f (i.e. 1.75 GHz)2f (i.e. 3.5 Gbps)2f (i.e. 3.5 GHz)8f (i.e. 14.0 Gbps)WCK_tWCK_cDDR WCKQDR WCK2.5 CLOCKING (contd)Figure 1 GDDR6 Clocking and Interface Relations
46、hipJEDEC Standard No. 250Page 72.5 CLOCKING (contd)Clock PhaseOscillatorQDCA9:0CMD/ADD DRAM QDQBDATADQearly/lateReceiverD QWCKintDQDRAM PLL/DLLQDDQPhase detector/corelogic early/late fromFor 8 data bitsControllerGDDR6 SGRAMPLL optionalclockData Tx/RxWCK_t/(6 GHz orCK_t/CK_c(1.5 GHz)ADD/CMD sampled b
47、y CK_t/CK_c as DDRADD/CMD centered with CK_t/CK_ccalibration dataPhase accumulatorControllerClock PhaseController(12 Gbps)corecore(3 GHz or 1.5GHz)D QWCK2CKAlignmentTo EDC pin/2 orWCK_c(3 Gbps)/43 GHz)Figure 2 Block Diagram of an example clock systemJEDEC Standard No. 250Page 83 INITIALIZATION3.1 PO
48、WER-UP SEQUENCEGDDR6 SGRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The Mode Registers do not have RESET default values, except for CABI, CA termination, and the EDC hold pattern. If the mode regi
49、sters are not set during the initialization sequence, it may lead to unspecified operation.1) Apply power to VPP. Apply power to VDDat the same time or after power is applied to VPP. Apply power to VDDQat the same time or after power is applied to VDD. VPPmust be equal to or higher than VDDat all times the device is powered up except during power-off sequence.2) Apply VREFCat same time or after power is applied to VDDQ, or pull VREFC LOW to select internal VREFC.3) The voltage levels on all signal balls must be less than or equal to VDDand VDDQon one side and must
