1、JEDEC STANDARD Gunning Transceiver Logic (GTL) Low-Level, High Speed Interface Standard for Digital Integrated Circuits JESD8-3A (Revision of JESD8-3, November 1993) MAY 2007 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, rev
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7、ll (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to cha
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10、 JEDEC Standard No. 8-3A Page 1 GUNNING TRANSCEIVER LOGIC (GTL) LOW-LEVEL HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS (From JEDEC Board Ballots, JCB-93-11A and JCB-07-24, formulated under the cognizance of the JC-16 Committee on Interface Technology.) 1 Scope This standard defines
11、the dc input and output specifications for a low-level, high-speed interface for integrated circuits. 1.1 Standard Specifications Interface specifications for this standard are defined in Tables 1 and 2. Input specification requirements typically imply an input comparator stage operating about the s
12、pecified reference voltage of 0.8 volt nominal. Output specifications include requirements for both an open-drain output stage requiring external termination and for an active-pullup, active-pulldown output stage that does not require external termination. In both cases the output high level is dete
13、rmined by a VTTor VDDQvoltage of 1.2 volts nominal. 1.1.1 Terminated Case In the terminated case the output device is typically an open-drain MOS transistor. The output is returned to the VTTtermination voltage through a termination resistance. 1.1.2 Unterminated Case In the unterminated case the ou
14、tput buffer has both an active-pullup and an active-pulldown transistor. For this case the nominal 1.2 volts is normally connected to a device pin (VDDQ) to supply the upper level return for the pullup transistor such that, under no-load conditions, the output would typically pull to the VDDQvoltage
15、. JEDEC Standard No. 8-3A Page 2 2 Application notes 2.1 Applicability to Alternative Voltage Level Systems GTL-compatible devices are expected to be used in systems with several VDDpower supply voltages including VDD= 5 volts, 3.3 volts and 2.X volts, thereby preserving a consistent interface level
16、 specification through many generations of devices and power supply standards. Signal pin interconnection with devices operating with other than GTL/ I/O standard specifications will require appropriate translation circuitry. Table 1 GTL*Standard DC Operating Specifications for Terminated Case Symbo
17、l Parameter Test Condition Min Typical (2) Max Units VTTTermination Voltage - 1.14 1.2 1.26 V VREF(1) Reference Voltage - (2/3)VTT- 2% 0.8 (2/3)VTT+2% V VIHHigh-Level Input Voltage - VREF+ 0.05 0.83 - V VILLow-Level Input Voltage - - 0.77 VREF- 0.05 V VOLLow-Level Output Voltage IOL= 40 mA - 0.2 0.4
18、 V IOOutput Leakage Current VSS VOUT VTT Output Off - - + 10 V IIInput Leakage Current VSS VIN VTT- - + 5 V NOTE 1 VREFmay be generated on or off the chip, but must track the termination voltage VTT. VREFand/or VTTmay be device input pins. NOTE 2 Except for VTTand VREF, the typical values are shown
19、for information only; they are not a requirement. *GTL has been patented under US Patent Number 5,023,488 dated June 11, 1991. The patent relates to CMOS drivers and receivers for low voltage swing and low power dissipation. The patent owner has agreed to license the patent under RAND terms as requi
20、red by JEDEC. JEDEC Standard No. 8-3A Page 3 2 Application notes (contd) 2.1 Applicability to Alternative Voltage Level Systems (contd) Table 2 GTL Standard DC Operating Specifications for Unterminated Case Symbol Parameter Test Condition Min Nom Max Units VDDQ(1) Output Buffer Supply Voltage - 1.14
21、 1.2 1.26 VREF(2) Reference Voltage - (2/3)VDDQ- 2% 0.8 (2/3)VDDQ- 2% V VIHHigh-Level Input Voltage - VREF+ 0.05 - - V VILLow-Level Input Voltage - - - VREF- 0.05 V VOLLow-Level Output Voltage IOL= 4 mA(3) - - 0.4 V VOH(4) High-Level Output Voltage IOH= 4 mA VDDQ- 0.4 - VDDQV IOOutput Leakage Curren
22、t VSS VOUT VDDQOutput Off - - + 10 V IIInput Leakage Current VSS VIN VDDQ- - + 5 V NOTE 1 VDDQis connected to one or more pins on the device and used internally on the chip to set the output value of VOH. VDDQmay also be used external to the chip to set the value of the output pin bus when the outpu
23、t is in the high-Z off condition. NOTE 2 VREFmay be generated on or off the chip but must track the VDDQvoltage. VREFmay be a device input pin. NOTE 3 This value of IOLis a lower limit of this standard. Other values of IOLabove this value are acceptable and considered to be encompassed within this s
24、tandard. NOTE 4 At the test condition of IOH, the VOHvalue establishes the upper voltage level requirements of the output pull-up transistor. This test condition is not intended to establish operating noise margins. The output VOHmay approach the VDDQrail when the active output is unloaded. JEDEC St
25、andard No. 8-3A Page 4 Annex A (informative) Differences between JESD8-3A and JESD8-3 This table briefly describes most of the changes made to entries that appear in this standard, JESD8-3A, compared to its predecessor, JESD8-3 (November 1993). If the change to a concept involves any words added or
26、deleted (excluding deletion of accidentally repeated words), it is included. Some punctuation changes are not included. Page Description of change 2 Changed footnote from: GTL has been patented. The patent relates to CMOS drivers and receivers for low voltage swing and low power dissipation. There i
27、s a one-time only licensing fee of not more than $10,000 required of semiconductor suppliers only. US Patent Number 5,023,488 dated June 11, 1991. To: GTL has been patented under US Patent Number 5,023,488 dated June 11, 1991. The patent relates to CMOS drivers and receivers for low voltage swing an
28、d low power dissipation. The patent owner has agreed to license the patent under RAND terms as required by JEDEC. 2 Table 1: Changed VILvalue for max. from: VREF+ 0.05 to VREF- 0.05 per errata dated September 9, 1998, typographical error. 3 Table 2: Changed VILvalue for max. from: VREF+ 0.05 to VREF
29、- 0.05 per errata dated September 9, 1998, typographical error. Rev. 9/02 Standard Improvement Form JESD8-3A The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit c
30、omments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 2500 Wilson Blvd. Suite 220 Arlington, VA 22201-3834 Fax: 703.907.7583 1. I recommend changes to the
31、following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date:
