1、EIA JESDB-6 75 W 3234600 0562354 L9b W o I EIA/ JEDEC STAN DA R D High Speed Transceiver Logic (HSTL) A 1.5 V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits EINJl3SD8-6 AUGUST 1995 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA JESDB-6 95 3234b00
2、0562355 O22 NOTICE EWJEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. EIMJEDEC Standards and Publications are designed to serve the public
3、interest through eliminating misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need Existence of such standards shall not
4、in any respect wedude any member or nonmember of JEDEC fiom manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or inkmationa
5、lly. EIA/JEDEC Standards and Publications are adopted without regard to whether their adoption may involve patents or articles, materials, or processes. By such action, EWJEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJED
6、EC Standards or Publications. The information included in EWJEDEC Standards and Publications represents a sound approach to product specification and application, principally fiom the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby an EWJEDEC Sta
7、ndard or Publication may be further processed and ultimately becomes an EIA Standard. inquiries. comments, and suggestions relative to the content of this EWJEDEC Standard should be addressed to the JEDEC Executive Secretary at EH Headquarters, 2500 Wilson Boulevard, Arlington, VA 2220 1. (From JEDE
8、C Council ballot JCB-94-64, formulated under the cognizance of JEDEC JC-16 Committee on Elcctrical Interface and Power Supply Standards for Electronic Components.) Published by OELECTRONIC TNDUSTRIES ASSOCIATION 1995 Engineering Department 2500 Wilson Boulevard Arlington, VA 2220 1 “Copyright“ does
9、not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of the JEDEC Publication 2 1 “Manual of Organization and Procedure“. PRICE: Please refer to the current Catalog of EIA, JEDEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call
10、 Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights reserved EIA JESDB-6 75 3234600 05623.56 T6 This document is copyrighted by the EIA and may not be reproduced without permission. Organizations may obtain permission to reproduce
11、a limited number of copies through entering into a license agreement. For information, contact: Global Engineering Documents 15 Inverness Way East Englewood, CO 80 1 12-5704 or call U.S.A. and Canada 1-800-854-7179, International (303) 397-7956 DONT VIOLATE THE LAW! EIA JESDB-b 95 W 3234b00 0562357
12、9T5 = JEDEC STANDARD NO. 8-6 HIGH SPEED TRANSCEIVER LOGIC (HSTL) A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS 1 Scope 1.1 Standard structure 1.2 Rationale and assumptions 2 Supply voltage and logic input levels 2.1 Supply voltage levels 2.2 Single end
13、ed input parametrics 2.3 Differential input parametrics 3 HSTL output buffers 3.1 HSTL Class I output buffers 3.1.1 Push-pull output buffer for unterminated loads 3.1.2 Push-pull output buffer for symmetrically paralle, terminated loads ( 3.1.3 HSTL Class I output ac conditions 3.2 HSTL Class II out
14、put buffers 3.2.1 Push-pull output buffer for externalh; source series terminated loads 3 7 2 Push-pull output buffer for symmetrtes. These loads are intended to produce a clean, replicable test result that can be easily correlated to simulation data and can be accurately derated to other use enviro
15、nments. It should be noted that signal timing, although out of necessity is actually measured at the end of the T- line that runs from the device under test to the tester VOs, is always referenced to the output pin of the device under test. Signal propagation delay through the T-line time is therefo
16、re subtracted out of the actual measurement. The influence of the lumped capacitance at the end of the T-line on sitgal rise and fall time is preserved. Although line length influences the power dissipation of the output buffers of the device under test it is not germane to this standard. 3.1 HSTL C
17、lass I output buffers 3.1.1 Push-pull output buffer for unterminated loads NOTES 2 I0,-8mA 3 The dc value of VE, applied to the receiving device is expected to be set to about V,1-,y/2 of the sending device in this case. EIA JESDB-b 75 m 3234600 0562365 T7L m Synliol V, (dc V, (dc 1 JEDEC STANDARD N
18、o. 8-6 Page 7 Parameter Min. Mar. Units Notes DC output logic high Vnno-0 4 V I DC output logic 1014 o 4 V 7 Figure 3.1-a - An example HSTL unterminated output load 3.1.2 Push-pull output buffer for symmetrically parallel terminated loads (VTT = VDDQ/ 2) NOTES 3 The dc value of VE! applied to the re
19、ceiving device is expected to be set to about VDDQ/2 of the sending device in this case. EIA JESDB-b 95 323qbOO 05b23bb 908 Symbol VOH (ac VOL (ac) JEDEC STANDARD NO. 8-6 Page 8 Condition Value Units Notes Minimum output pull-up under ac test load VDDQ - 0.50 V 1 Output timuig measurement reference
20、level VDDO* V 1,2 Maximum output pull-doun under ac test load 0.50 V Vnm CLOAD 2 20 pf Figure 3.1-b - An example HSTL symmetrically parallel terminated output load and Class I HSTL ac test load diagram 3.1.3 HSTL Class I output ac test conditions This testing regimen is used to veri- HSTL Class I ty
21、pe output buffers (buffers designed for unterminated or lumped-capacitance loads and symmetrically terminated loads). NOTES 1 The VDDQ of the device under test is referenced. 2 Used as the output signai timing reference point. VOH(ac) and VoL(ac) are not used as output timing reference points. EIA J
22、ESDB-6 95 3234600 0562367 BYY Symbol Parameter V, (dc) VOL (dc) DC output logic high DC output logic low JEDEC STANDARD NO. 8-6 Page 9 Min. Mar. Units Notes V,-0.4 v 1 0.4 V - 7 3.2 HSTL Class II output buffers 3.2.1 Push-pull output buffer for externally source series terminated loads NOTES 1 IO“ l
23、6mA 2 10, L 1- 16mAl 3 The dc value of VE, applied to the receiving device is expected to be set to about V,Q/2 of the sending device in this case. - WDQ - WDQ/2 SOR vREF=vDDQ/2 - CLOAD 120 pf Figure 3.2-a - An example HSTL source series terminated output load JEDEC STANDARD NO. 8-6 Page 10 Symbol P
24、arameter Min. Max. Units V, (dc) DC output logic high V,-0.4 V VOL (dc) DC output logic low 0.4 V Notes 1 7 - NOTES 4 3 The dc value of VEF applied to the receiving device is expected to be set to about V,y/2 of the sending device in this case. mDQ VREF Device Under Test vrs=vDDQ/2 I Y - I= wDQ/2 CL
25、OAD 2 20 pf Figure 3.2-b - An example HSTL symmetrically double parallel terminated output load and Class II HSTL ac test load diagram 3.2.3 HSTL Class II output test conditions This testing regimen is used to veri& HSTL Class II type output buffers ( buffers designed for externally source series te
26、rminated or symmetrically double parallel terminated loads). EIA JESDB-6 95 = 3234600 05623b9 bL7 Symbol V, (ac) VOL (ac) JEDEC STANDARD No. 8-6 Page 11 Condition Value Units Notes Muiunum output pull-up under ac test load VDDQ - 0.50 V I Maximum output pull-down under ac test load 0.50 v Output tim
27、ing measurement reference level v,D(J/? V I. I Table 3.2-c - AC test conditions Symbol VOH (dc) VOL (dc) Parameter Min. Max. Units Notes DC output logic high V,-0.4 V 1 DC output logic low 0.4 v 7 NOTES 1 The VDDq of the device under test is referenced. 2 Used as the output signal timing reference p
28、oint. VOH(ac) and V,(ac) are not used as output timing reference points. 3.3 HSTL Class III output buffers 3.3.1 Push-pull output buffer for asymmetrically parallel terminated loads (V, = VDDQ) NOTES 3 The dc value of Vu, applied to the receiving device is expected to be set to about 0.90 V in this
29、case. EIA JESDB-6 95 W 3234600 0562370 339 W Symbol V, (ac) VOL (ac) JEDEC STANDARD NO. 8-6 Page 12 Units Notes Condition Valuc Minimum output pull-up under ac test load ida I Maximum output pull-doum under ac test load i) 50 V Output timing measureniznt reference level u.90 V I,? I 1 I vREF=o.9ov U
30、OAD 2 20 pf Figure 3.3-a - An example HSTL asymmetrically parallel terminated output load and Class III HSTL ac test load diagram 3.3.2 HSTL Class III output ac test conditions This testing regimen is used to verifi. HSTL Class III type output buffers ( buffers designed for asymmetricall. parallel t
31、erminated loads). NOTES 1 Output high voltage is expected to settle .en. near VDDq due to the pull-up termination resistor. . 2 Used as the output signal timing reference point. VoH(ac) and VOL(“) are not used as output timing reference points. EIA JESDB-6 75 3234600 0562373 275 S,YmlOl Parameter “l
32、in, c ). I . Max. V, (dc) DC output logic hgh v,-o 4 VOL (dc) DC output logic IOU 04 JEDEC STANDARD NO 8-6 Page 12 Units- Notes V 1 V 7 3.4 HSTL Class IV output buffers 3.4.1 Push-pull output buffer for asymmetrically double parallel terminated loads (Vm = VDDQ) NOTES 2 I, L 1- 48 mAl (VTT = VDDQ. R
33、T1 = 50 Q. RT2 = 50 Q) 3 The dc value of V, applied to the receiving device is expected to be set to about 0.90 V in this case. VREF Device Under Test - 0.9ov son I vTr=vDDQ CLOAD2u)pf Figure 3.4-a - An example HSTL asymmetrically double parallel terminated output load and class IV HSTL ac output lo
34、ad diagram 3.4.2 HSTL Class IV output ac test conditions This testing regimen IS used to verifi HSTL Class IV type output buffers (push-pull output buffers designed for asynmetricall!f double parallel terminated loads). EIA JESD8-6 95 3234600 0562372 101 b Symbol V, (ac) JEDEC STANDARD NO. 8-6 Page
35、14 Condition Value Units Notes Minimum output pull-up under ac test load n/n I VOL (ac) Maximum output pull-down under ac test load O 50 V Output timing measurement reference level o YO V I.? NOTES 1 Output high voltage is expected to settle ve- near VDDq due to the pullup termination resistor. 2 Used as the output signal timing reference point. V,(ac) and VoL(ac) are not used as output timing reference points. EIA JESD8-6 95 m 3234600 O562373 048 m
