1、 TIA-899-2002 APPROVED: FEBUARY 26, 2002 REAFFIRMED: DECEMBER 7, 2012 TIA-899 March 2002Electrical Characteristics of Multipoint-Low-Voltage Differential Signaling (M-LVDS) Interface Circuits for Multipoint Data Interchange NOTICE TIA Engineering Standards and Publications are designed to serve the
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19、TS HEREOF, AND THESE CONTENTS WOULD NOT BE PUBLISHED BY TIA WITHOUT SUCH LIMITATIONS. TIA/EIA-899 ELECTRICAL CHARACTERISTICS OF MULTIPOINT-LOW-VOLTAGE DIFFERENTIAL SIGNALING (M-LVDS) INTERFACE CIRCUITS FOR MULTIPOINT DATA INTERCHANGE Table of Contents 1 SCOPE 1 2 DEFINITIONS, SYMBOLS, AND ABBREVIATI
20、ONS 1 3 APPLICABILITY 2 3.1 General applicability 2 3.2 Signaling rate . 4 3.3 Transmission distance 5 4 ELECTRICAL CHARACTERISTICS . 5 4.1 Driver characteristics 5 4.2 Receiver characteristics 12 4.3 Interchange input impedance. 15 4.4 Interconnecting media electrical characteristics . 20 5 SYSTEM
21、CONSIDERATIONS. 20 5.1 Failsafe operation 20 5.2 Transient protection 21 5.3 Signal common (ground) 21 5.4 Noise budgeting. 23 ANNEX A (INFORMATIVE) 26 A.1 Interconnecting cable 26 A.2 Additional characteristics. 26 A.3 Length . 26 A.4 Typical cable characteristics 26 A.5 Cable length vs. signaling
22、rate guidelines 28 ANNEX B (INFORMATIVE) 30 ANNEX C (INFORMATIVE) 33 C.1 Related TIA/EIA standards 34 C.2 Other related interface standards 34 ANNEX D (INFORMATIVE) 35 List of Figures FIGURE 1 - MULTIPOINT APPLICATION OF M-LVDS INTERFACE CIRCUITS. 3 i TIA/EIA-899 FIGURE 2 TWO-CIRCUIT APPLICATION OF
23、M-LVDS. 3 FIGURE 3 - MAXIMUM SIGNALING RATE CALCULATION. 4 FIGURE 4 DRIVER OUTPUT VOLTAGE AND CURRENT DEFINITIONS. . 5 FIGURE 5 - DRIVER OUTPUT SIGNALING SENSE. 6 FIGURE 6 - DIFFERENTIAL OUTPUT VOLTAGE TEST CIRCUIT. 7 FIGURE 7 - OUTPUT VOLTAGE TEST CIRCUIT. 8 FIGURE 8 - DRIVER OFFSET VOLTAGE TEST CI
24、RCUIT. 8 FIGURE 9 - DRIVER SHORT-CIRCUIT TEST CIRCUIT. 9 FIGURE 10 - DRIVER OUTPUT SIGNAL WAVEFORM. . 11 FIGURE 11 - DYNAMIC DRIVER OUTPUT BALANCE MEASUREMENT 12 FIGURE 12 - RECEIVER VOLTAGE AND CURRENT DEFINITIONS. . 12 FIGURE 13 - RECEIVER DIFFERENTIAL INPUT VOLTAGE THRESHOLD REQUIREMENTS. 13 FIGU
25、RE 14 TYPE-1 RECEIVER INPUT VOLTAGE RANGE. 14 FIGURE 15 TYPE-2 RECEIVER INPUT VOLTAGE RANGE. 15 FIGURE 16 - ALLOWED STEADY-STATE INPUT CURRENT VERSUS INPUT VOLTAGE 16 FIGURE 17 - DIFFERENTIAL INPUT CURRENT TEST 17 FIGURE 18 - VOLTAGE AND CURRENT DEFINITIONS FOR TERMINATING INTERCHANGES. 18 FIGURE 19
26、 - OPTIONAL GROUNDING ARRANGEMENT A 22 FIGURE 20 - OPTIONAL GROUNDING ARRANGEMENT B 23 FIGURE 21 - OPTIONAL GROUNDING ARRANGEMENT C 23 FIGURE 22 - SIGNALING RATE VERSUS CABLE LENGTH FOR A 5% EYE-PATTERN JITTER. 29 FIGURE 23 - VOLTAGE RANGES OF DIFFERENTIAL INTERFACE STANDARDS. 34 List of Tables TABL
27、E 1 - RECEIVER INPUT VOLTAGE THRESHOLD REQUIREMENTS 13 TABLE 2 - TYPE-1 RECEIVER NOISE BUDGET EXAMPLE 24 TABLE 3 - TYPE-2 RECEIVER NOISE BUDGET EXAMPLE 24 ii TIA/EIA-899 FOREWORD (This foreword is not part of this Standard) This Standard was formulated under the cognizance of TIA Subcommittee TR-30.
28、2 on Data Transmission Interfaces. This Standard specifies low-voltage differential signaling drivers and receivers for data interchange across half-duplex or multipoint data bus structures. M-LVDS is capable of operating at signaling rates up to 500 Mb/s. Devices may be designed for signaling rates
29、 less than 500 Mb/s, 100 Mb/s for example, when economically or technically required for that application. This Standard was developed in response to a demand from the data communications community for a general-purpose high-speed balanced interface standard for multipoint applications. The voltage
30、levels are specified such that maximum flexibility would be provided, while providing a low-power high-speed differential interface. Driver output characteristics are independent of power supply, and may be designed for standard 5 V, 3.3 V or lower power supplies. The requirements of this standard m
31、ay be implemented with any integrated circuit technology, such as BiCMOS, CMOS, or GaAs technology. The low-voltage (565-mV typical) swing reduces power dissipation and the potential for radiated emissions. Differential signaling provides multiple benefits over single-ended signaling, notably common
32、mode rejection and magnetic field cancellation. The electrical signal levels are similar to those described in the TIA/EIA-644 standard, and will interoperate with certain interchange circuits and signaling rates. This Standard includes four informative Annexes. Annex A provides guidelines for appl
33、ication, addressing signaling rate and cable length issues. Annex B covers printed-circuit board guidelines. Annex C provides comparison information with other interface standards and references to this Standard. Annex D provides a derivation of the formula for approximating the bus loading effects.
34、 iii TIA/EIA-899 1 SCOPE This Standard specifies the electrical characteristics of low-voltage differential signaling interface circuits that may be employed when specified for the interchange of binary signals between equipment sharing a common data interchange circuit. The electrical characteristi
35、cs of the circuit are specified in terms of required voltage and current values obtained from direct measurements of the driver and receiver components at the multipoint line interface points. The logic function of the driver and the receiver or the communication protocol is not defined by this Stan
36、dard, as it is application dependent. Optional receiver input characteristics are specified to allow idle-line fail-safe or Wired-or signaling at slower signaling rates. Minimum electrical characteristics of the transmission media and interconnection requirements are provided, where media refers to
37、printed circuit board traces (backplane) or cables. Further guidelines for application of this Standard are provided in the annexes. It is intended that this Standard will be referenced by other standards that specify the complete interface (i.e., connector, pin assignments, function) for applicatio
38、ns where the electrical characteristics of a multipoint low-voltage differential interface circuit is required. The referencing standard(s) also specify other characteristics of the interface (such as signal quality, protocol, bus structure, and timing) essential for proper operation across the inte
39、rface. When this Standard is referenced by other standards or specifications, it should be noted that certain options are available. The author of those standards and specifications must determine and specify those optional features that are required for that application. 2 DEFINITIONS, SYMBOLS, AND
40、 ABBREVIATIONS For the purposes of this Standard, the following definitions, symbols, and abbreviations apply: Bus. A bus is a common pathway or channel, between multiple devices. A single M-LVDS interchange circuit. Common-mode voltage. The common-mode voltage is equal to one half of the vector sum
41、 of the voltages between each conductor of a balanced interchange circuit and ground. The common-mode voltage is the sum of ground potential difference, driver common-mode output voltage (driver offset voltage), and longitudinally coupled noise. Idle line. An idle line is a multipoint line with all
42、drivers off. 1 TIA/EIA-899 Inter-symbol interference. Inter-symbol interference is the time displacement of a state transition due to a new wave (subsequent signal) arriving at the receiver site before the previous wave has reached its final value. Jitter. Jitter is the time variation of the instant
43、 a binary signal crosses a threshold (state transition) from the ideal occurrence. M-LVDS. Multipoint-Low-Voltage Differential Signaling Multipoint. Multipoint refers to a communications line (network) that provides a path from any one location to one or more. Multipoint line. A multipoint line is a
44、 single line that interconnects two or more devices. Point-to-Point. Point-to-point refers to a communications line that provides a unidirectional path from one location to another (point A to point B). Signaling rate. The signaling rate of a line, is the number of transitions (voltage or frequency
45、changes) that are made per second expressed in the units b/s (bits per second). It may be different from the equipments data transfer rate, which employs the same units. Transition time. Unless otherwise specified, the transition time is the 10%-to-90% rise or fall time of a binary signal. Unit Inte
46、rval. The unit interval (UI or tUI) is the mathematical inverse of the signaling rate. *. * (star) represents the opposite input condition for a parameter. For example, the symbol Q represents the receiver output state for one input condition, while Q* represents the output state for the opposite in
47、put state. 3 APPLICABILITY 3.1 General applicability The provisions of this Standard may be applied to the circuits employed at the interface between equipment where information being conveyed is in the form of binary signals. The interface circuit (shown schematically in Figure 1) consists of a bal
48、anced interconnecting media terminated at the ends by transmission-line termination impedance (designated as Zt). There may be as many as thirty-two M-LVDS circuits connected to the media at the interchange points. This Standard specifies the electrical characteristics of the interchange points mark
49、ed A0, B0, and C0; A1, B1, and C1; and so on. The interconnected circuits may be a driver (output only), receiver (input only), or transceiver (input and output). 2 TIA/EIA-899 A0A1AnB0B1BnZtZtBalanced InterconnectingMediaC0C1CnCircuit 0 Circuit 1 Circuit nFigure 1 - Multipoint application of M-LVDS interface circuits. ZtZtA0A1B0B1C0C1Balanced InterconnectingMediaCircuit 0 Circuit 1Figure 2 Two-circuit application of M-LVDS. The M-LVDS interface is intended for use where any of the following conditions prevail: a) A multipoint connection is desired. b) The signaling rate is too
