BS EN 60191-6-20-2010 Mechanical standardization of semiconductor devices General rules for the preparation of outline drawings of surface mounted semiconductor device packages Meau.pdf
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1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationMechanical standardization of semiconductor devicesPart 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Measuring met
2、hods for package dimensions of small outline J-lead packages (SOJ)BS EN 60191-6-20:2010National forewordThis British Standard is the UK implementation of EN 60191-6-20:2010. It isidentical to IEC 60191-6-20:2010.The UK participation in its preparation was entrusted to Technical CommitteeEPL/47, Semi
3、conductors.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions of acontract. Users are responsible for its correct application. BSI 2010ISBN 978 0 580 64566 2ICS 31.080.01Compliance
4、 with a British Standard cannot confer immunity fromlegal obligations.This British Standard was published under the authority of the StandardsPolicy and Strategy Committee on 31 December 2010.Amendments issued since publicationAmd. No. Date Text affectedBRITISH STANDARDBS EN 60191-6-20:2010EUROPEAN
5、STANDARD EN 60191-6-20 NORME EUROPENNE EUROPISCHE NORM October 2010 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Management Centre: Avenue Marnix 17, B - 1000 Brussels 2010 CENELEC - A
6、ll rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 60191-6-20:2010 E ICS 31.080.01 English version Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semicon
7、ductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ) (IEC 60191-6-20:2010) Normalisation mcanique des dispositifs semiconducteurs - Part 6-20: Rgles gnrales pour la prparation des dessins dencombrement des botiers pour dispositifs semiconducteurs p
8、our montage en surface - Mthodes de mesure pour les dimensions des botiers sortie en J (SOJ) de faible encombrement (CEI 60191-6-20:2010) Mechanische Normung von Halbleiterbauelementen - Teil 6-20: Allgemeine Regeln fr die Erstellung von Gehusezeichnungen von SMD-Halbleitergehusen - Messverfahren fr
9、 Gehusemae von kleinen Gehusen mit J-frmigen Anschlssen (SOJ) (IEC 60191-6-20:2010) This European Standard was approved by CENELEC on 2010-10-01. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status
10、of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A
11、version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croat
12、ia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom. BS EN 60191-6-20:2010
13、EN 60191-6-20:2010 - 2 - Foreword The text of document 47D/771/FDIS, future edition 1 of IEC 60191-6-20, prepared by SC 47D, Mechanical standardization for semiconductor devices, of IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 601
14、91-6-20 on 2010-10-01. Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent rights. The following dates were fixed: latest date by which the EN has to
15、 be implemented at national level by publication of an identical national standard or by endorsement (dop) 2011-07-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2013-10-01 Annex ZA has been added by CENELEC. _ Endorsement notice The text of the Int
16、ernational Standard IEC 60191-6-20:2010 was approved by CENELEC as a European Standard without any modification. _ BS EN 60191-6-20:2010- 3 - EN 60191-6-20:2010 Annex ZA (normative) Normative references to international publications with their corresponding European publications The following refere
17、nced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. NOTE When an international publication has been modified by common mo
18、difications, indicated by (mod), the relevant EN/HD applies. Publication Year Title EN/HD Year IEC 60191-4 - Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages EN 60191-4 - IEC 60191-6 - Mech
19、anical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages EN 60191-6 - BS EN 60191-6-20:2010 4 60191-6-20 IEC:2010 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-20: General rules for t
20、he preparation of outline drawings of surface mounted semiconductor device packages Measuring methods for package dimensions of small outline J-lead packages (SOJ) 1 Scope This part of IEC 60191 specifies methods to measure package dimensions of small outline J-lead-packages (SOJ), package outline f
21、orm E in accordance with IEC 60191-4. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendment
22、s) applies. IEC 60191-4, Mechanical standardization of semiconductor devices Part 4: Coding system and classification into forms of package outlines for semiconductor device packages IEC 60191-6, Mechanical standardization of semiconductor devices Part 6: General rules for the preparation of outline
23、 drawings of surface mounted semiconductor device packages 3 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 60191-6 apply. 4 Measuring methods 4.1 Description of measuring methods The measuring methods described in this standard are for dimension valu
24、es guaranteed to users on the basis of the following items. a) In general, measuring the dimensions shall be made with the semiconductor packages mounted on a printed circuit board as the guarantee is made to user. b) In general, measurement may be made either by hand or automatically. c) Even if a
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