1、CECC CECC*90*104- 029*ISSUE*2 * = L974499 0044295 T22 Page 1 NEDER LANDS ELEKTROTECHNISCH COMITE POSTBOX 5059 2600 GB DELFT Total number of pages: 12 This specification is also available from Nederlandse Philips Bedrijven B.V. CECC 90 104-029 ISSUE 2 ELECTRONIC COMPONENTS OF ASSESSED QUALITY IN ACCO
2、RDANCE WITH: GS: CECC 90 O00 Issue 3. SS: CECC 90 100 Issue 3. FS: CECC 90 104 Issue 2. Detail Spec: N L-CECC 90 104-029 Issue: 2 I ssued : December 1989 OUTLINE AND DIMENSIONS: I IEC 191-2 1 050 G09/A76 G1 TERMINAL CONNECTIONS: See item 1.3 of this specification DETAIL. SPECIFICATION FOR DI G ITA L
3、 I NTEG RATED CI RCU ITS IN ACCORDANCE WITH FS 90 104 H EC/H E F 4035B 4-bit universal shift register TYPICAL CONSTRUCTION: Silicon rnonolithic local oxidation CMOS integrated circuit, cavity/non- cavity PBC kages. CAUTION: STATIC SENSITIVE DEVICE 1 ASSESSMENT LEVELS: P, Y, L REMARKS I I 1 Informati
4、on about manufacturers who have components qualified to this detail specification is 1 available in the current CECC O0 200: Qualified Products List. Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without
5、 license from IHS-,-,-Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft This specification is also available from Nederlandse Philips Bedrijven B.V. Page 2 of 12 CECC 90 104-029 ISSUE 2 1 TYPE DESCRIPTION 1.1 Function The HEC/HEF4035B are fully synchronous edge-triggered4-bit shift regist
6、ers with a clock input (CP), four synchronous parallel data inputs (Po to PQ), two synchronous serial data inputs (J, I, a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to 031, a true/comp- lement input (T/C) and an overriding asynchronous master rese
7、t input (MR). Each register is of a D-type master-slave flip-flop. Operation is synchronous (except for MR) and is edge-triggered on the LOW to HIGH transition of the CP input. When PE is HIGH, data is loaded into the register from Po to P3 on the LOW to HIGH transition of CP. When PE is LOW, data i
8、s shifted into the first register position from J and and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J and K. When J = HIGH and K = LOW the first stage is in the toggle mode. When J = LOW and = HI
9、GH the first stage is in the hold mode. The outputs (O0 to 03) are either inverting or non-inverting, depending on T/Cstate. With T/c HIGH, 00 to O3 are non-inverting (active HIGH) and when T/C is LOW, 00 to O3 are inverting (active LOW). A HIGH on MR resets all four bit positions (O0 to O3 = LOW if
10、 T/c= HIGH, 00 to O3 = HIGH if TIC= LOW) independent of all other input conditions. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for Resale
11、No reproduction or networking permitted without license from IHS-,-,-CECC CECC*SO*L04- 029*ISSUE*2 * m 1974499 0044297 8T5 m Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft This specification is also available from Nederlandse Philips Bedrijven B.V. Page 3 of 12 1.1.1 Function tables Se
12、rial operation first stage I inputs CP J MR fHHL fLLL fHLL fLHL XXXH output mode of operation H D flip-flop L D flip-flop 00 toggle 00 nochange L reset Parallel operation I I inputs I outputs I I -1 f = positive-going transition H = HIGH state (the more positive voltage) L = LOW state (the less posi
13、tive voltage) X = state is immaterial CECC 90 104 -029 ISSUE 2 T/C= HIGH; PE = LOW T/C= HIGH; PE = HIGH; MR = LOW Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-CECC CECC*SO*L
14、4- 023*ISSUE*2 * m 2774499 0044298 731 m Nederlands Elektrotechnisch Comite Page 4 1 CECC 90 104-029 Postbox 5059 2600GB Delft This specification is also available from Nederlandse Philips Bedrijven B.V. 1 of12 ISSUE 2 1.1.2 Functional diagram 9 10 11 12 PO P1 p2 p3 c - PARALLEL ENABLE CIRCUITRY PE
15、J K . :P D1 D2 D3 CD SHIFT REGISTER 4-BITS CP blR (1 TRUE /COMPLEMENT CIRCUITRY TIC O0 O1 o2 o3 7269535.3 1 15 14 13 Fig. 1 Functional diagram. 1.1.3 Pinning information PE parallel enable input CP Po to P3 J K parallel data inputs first stage J-input (active HIGH) first stage K-input (active LOW) T
16、IC MR 00 to O3 clock input (LOW to HIGH edge- triggered) true/comp Grnent input master reset input buffered parallel outputs Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-CEC
17、C CECC*90*104- 029*ISSUE*2 * = 1974499 0044299 b78 Nederlands Elektrotechnisch Comite Page 5 CECC 90 104-029 Postbox 5059 2600GB Delft This specification is also available from Nederlandse Philips Bedrijven B.V. of 12 I ISSUE2 r +Do L IY o U a z U O O Copyright CENELEC Electronic Components Committe
18、e Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-CECC CECC*90*L04- 029*ISSUE*2 *Y 1974499 0044300 LLT - Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft This specification is also available from Nederlandse Philip
19、s Bedrijven B.V. Page 6 of 12 1.3 Terminal identification, type designation and marking 1.3.1 Terminal identification (top view) Fig. 3 Pinning diagram. 1.3.2 Type designation HEF = limited temperature range HEC = full temperature range. 1.3.3 Marking See item 2.5 and 2.6 of CECC 90 000. 1.4 Orderin
20、g information When ordering please state the following: a : Quantity b : Manufacturer c : Operating ambient temperature range (HEC or HEF) and device number d : Quality assessment level (P, Y or L) e : Optional, screening class (refer to CECC 90 000) f : Package code (P = plastic, D = ceramic and T
21、= mini-pack). 1.4.1 Ordering information example a : N (N = quantity required) b : Philips c : HEFXXX (XXX = device number) d:P e:B f :T. CECC 90 104-029 ISSUE 2 Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permi
22、tted without license from IHS-,-,-CECC CECC*90*304- 029*ISSUE*2 * 1974499 0044303 O56 This specification is also available from Nederlandse Philips Bedrijven B.V. I of12 Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft ISSUE 2 Page 7 unit CECC 90 104-029 conditions Output (source) curren
23、t HIGH Output (source) current HIGH I I I 5 4,64 -0,51 -0,36 10 IOHB -1,6 -1,3 -0,9 15 -4,2 -3,4 -2,4 5 -0,52 -0,44 -0,36 10 IOHB -1,3 -1,l -0,9 15 -3,6 -3,O -2,4 2 Additional to clause 1 of FS 90 104. LIMITING CONDITIONS (not for inspection purposes) 2.1 Maximum continuous current into any output I
24、 = 10 mA. 2.2 Maximum power dissipation per output Pmax = 100 mW. 2.3 Maximum power dissipation per package Temperature range: limited (for plastic and ceramic DI L) Ptot (max) = 500 mW. Derate linearly with 8 mW/K. Temperature range: full (ceramic DI L only) for Tamb = -55 to + 70 Oc for Tamb = + 7
25、0 to + 125 Oc Temperature range: limited (for plastic SO) Ptot(max) = 500 mW. Derate linearly with 8 mW/K. Ptot (ma?) = 400 mW. Derate linearly with 6 mW/K. 2.4 Transient energy rating 400 V. 3 Additional to clause 2 of FS 90 104. RECOMMENDED OPERATING CONDITIONS AND ASSOCIATED CHARACTERISTICS 3.1 R
26、ecommended operating conditions Applicable IDDA category (item 2.1) : MSI. 3.2 Static and dynamic characteristics 3.2.1 Static characteristics In compliance with item 2.6, note 3 of FS 90 104. I I I I parameter mA mA mA mA mA mA JO = 4,6 V; VI = O or 5 V /o = 9,5 V; VI = O or 10 V Vo=13,5V;V1=Oor 15
27、V /o = 4,6 V; VI = O or 5 V /o = 93 V; VI = O or 10 V /o = 13,5 V; VI = O or 15 V Tamb = 1 limited Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-CECC CECC*90*104- 029*ISSUE*2
28、 * m I1974499 0044302 T92 m Nederlands Elektrotechnisch Comite Page 8 CECC 90 104-029 Postbox 5059 2600GB Delft This specification is also available from Nederlandse Philips Bedrijven B.V. 340 140 100 300 130 100 230 100 80 230 100 80 210 100 70 170 90 70 120 60 40 120 60 40 of 12 ns 1 ns i ns ns ns
29、 i ns I ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 - ISSUE 2 3.2.2 Dynamic characteristics Vss = O V; Tamb = +25 OC; CL = 50 pF; input transition times 20 ns; load circuit: see 2.13 family specification; temperature range: full and limited. I parameter Propagation delays r CP On HIGH to
30、 LOW LOW to HIGH MR On HIGH to LOW LOW to HIGH T/C- On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH - VDD V 5 10 15 5 10 15 5 10 15 5 10 15 5 10 symbol min. + t LH I PHL I 1 PLH PH L 15 , 5 10 15 5 10 15 5 10 15 PLH TH L TLH WP. - 170 70 50 150 65 50 115 50 40 115 50 40 10
31、5 50 35 85 45 35 60 30 20 60 30 20 _ typical extrapolation maxl unit I formula 143 ns + (0,55 ns/pF) CL 59 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 123 ns + (0,55 ns/pF) CL 54 ns + (023 ns/pF) CL 42 ns + (0,16 ns/pF) CL 88 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/p F ) C L 32 ns + (0,16 ns/pF) CL 8
32、8 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF 32 ns + (0,16 ns/pF 78 ns + (0,55 ns/pF 39 ns + (0,23 ns/pF 27 ns + (O, 16 ns/pF 58 ns + (0,55 ns/pF 34 ns + (023 ns/pF 27 ns + (0,16 ns/pF 10 ns + (1,O ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/p F 1 C L 10 ns + (1,O ns/pF) CL 9 ns + (0,42 ns/p F C
33、L 6 ns + (0,28 ns/pF) CL Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-CECC CECC*SO*L04- 029*ISSUE*2 * 1974479 0044303 929 I I Nederlands Elektrotechnisch Comite Postbox 5059
34、 2600GB Delft Page 9 CECC 90 104-029 This specification is also available from Nederlandse Philips Bedrijven B.V. 1 of12 I ISSUE2 3.2.2 Dynamic characteristics (continued) parameter Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery time for MR Set-up times Pn - CP PE - CP J, - CP
35、Hold times P“ -) CP PE - CP J, -+ CP Maximum clock pulse frequency VDD V 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 symbol tWCPL WMRH RMR tSU tSU tSU thold thold thold fmax min. 80 40 30 50 30 20 50 40 25 40 25 15 50 35 30 55 35 25 25 20 20 15 10 5 10 10 10 5 12
36、15 - 40 20 15 25 15 10 20 15 10 5 O O 25 15 10 40 15 10 10 10 10 -5 -5 -5 -5 O O 10 25 30 - - max. - unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz M Hz MHz ns typical extrapolation formula see also waveforms Figs 4 and 5 Copyright CENELEC Electronic Component
37、s Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-CECC CECC*SO*L04- 029*ISSUE*2 * = 1974479 0044304 865 Nederlands Elektrotechnisch Comite Postbox 5059 2600GB Delft Page 10 CECC 90 104-029 This specification is also
38、available from Nederlandse Philips Bedrijven B.V. of 12 ISSUE 2 J I I 1 N N m i + Tarnt, = 25 OC; CL = 50 pF; input transition times 20 ns. parameter 1 VFD I typical formula for P (pw Dynamic power dissipation per package (Pl where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) X
39、(f0CL) =sum of outputs VDD = supply voltage (VI Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-CECC CECC*90*104- 029*ISSUE*2 * m 1974499 0044306 638 m I Nederlands Elektrotech
40、nisch Cornite Postbox 5059 2600GB Delft - - r 7 o2 right shift I 3 serial output This specification is also available from Nederlandse Philips Bedrijven B.V. VDD 01 O2 O3 P3 P2 Pi Po H E C/H E F4035B 00 T/C E J MR CP PE Vss J Page 12 of 12 3.3 Supplementary information 3.3.1 Application information
41、Some examples of applications for the HEC/HEF4035B are: Counters, registers, arithmetic-unit registers, shift-lefthhift-right registers. Serial-to-paral lel/parallel-to-serial conversions. Sequence generation. Control circuits. 0 Code conversion. left shift serial input VDD - right shift serial input reset clock CECC 90 104-029 ISSUE 2 left /right shift select h Fig. 6 Shift-lefthhift-right register. Copyright CENELEC Electronic Components Committee Provided by IHS under license with CECCNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
