1、 REVISIONSLTR DESCRIPTION DATE (YY-MM-DD) APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 11-02-01 David J. Corbett CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item
2、 drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 PMIC N/A PREPARED BY Thanh V. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Thanh V. Nguyen TITLE MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, OCTAL BUFFER AND
3、 LINE DRIVER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON YY-MM-DD 04-04-13 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04698 REV A PAGE 1 OF 9 AMSC N/A 5962-V031-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr
4、om IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04698 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance octal buffer and line driver with three-state outputs microcircuit, with an operating tempera
5、ture range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04698 - 01 X E Drawing Device t
6、ype Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 74HCT244-EP Octal buffer and line driver with three-state outputs, TTL compatible inputs 1.2.2 Case outline(s). The case outlines are as specified herein. Outline let
7、ter Number of pins JEDEC PUB 95 Package style X 20 MO-153 Plastic small-outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Go
8、ld flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 7.0 V Input clamp current (IIK) (VI 0 or VI VCC) . 20 mA 2/ Output clamp current (IOK) (VO 0 or VO VCC) . 20 mA 2/ Continuous output current (IO) (VO= 0 to VCC) 35 mA Continuous current through VCCor G
9、ND . 70 mA Storage temperature range (TSTG) . -65C to 150C Package thermal impedance (JA): 3/ X package . 83C/W _ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these o
10、r any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are
11、 observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04698 REV A PAGE 3 1.4 Reco
12、mmended operating conditions. 4/ 5/ Supply voltage range (VCC) . 4.5 V to 5.5 V Input voltage range (VI) . 0.0 V to VCC Output voltage range (VO) . 0.0 V to VCCMinimum high level input voltage (VIH): VCC= 4.5 V to 5.5 V . 2.0 V Maximum low level input voltage (VIL): VCC= 4.5 V to 5.5 V . 0.8 V Maxim
13、um input transition rise or fall time (t/v). 500 ns Operating free-air temperature range (TA) -40C to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packa
14、ges (Applications for copies should be addressed to the Electronic Industries Alliance, 3103 North 10thSt., Suite 240-S, Arlington, VA 22201-2107 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown i
15、n 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The max
16、imum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimensions. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). Th
17、e case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit an
18、d timing waveforms. The test circuit and timing waveforms shall be as shown in figure 5. 4/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The ma
19、nufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04
20、698 REV A PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCC Temperature, TA Device type Limits Unit Min Max High level output voltage VOH VI= VIHor VIL2/ IOH= -20 A 4.5 V 25C, -40C to 125C All 4.4 V VI= VIHor VIL2/ IOH= -6 mA 4.5 V 25C 3.98 -40C to 125C 3.7 Low le
21、vel output voltage VOL VI= VIHor VIL2/ IOL= 20 A 4.5 V 25C, -40C to 125C All 0.1 V VI= VIHor VIL2/ IOL= 6 mA 4.5 V 25C 0.26 -40C to 125C 0.40 Input current II VI= VCCor 0 V 5.5 V 25C All 100 nA -40C to 125C 1000 Three-state output leakage current IOZ VI= VIHor VIL2/ VO= VCCor 0 V 5.5 V 25C All 0.5 A
22、 -40C to 125C 10.0 Quiescent supply current ICC VI= VCCor 0 V IO= 0 A 5.5 V 25C All 8.0 A -40C to 125C 160.0 Quiescent supply current delta, TTL input levels ICC3/ One input at 0.5 V or 2.4 V Other inputs at 0.0 V or VCC5.5 V 25C All 2.4 mA -40C to 125C 3.0 Input capacitance CI 4.5 V to 5.5 V 25C, -
23、40C to 125C All 10 pF Power dissipation capacitance per buffer/driver CPD No load 25C All 40 typical pF Propagation delay time, A to Y tpd CL= 50 pF See figure 5 4.5 V 25C All 28 ns -40C to 125C 42 5.5 V 25C 25 -40C to 125C 38 CL= 150 pF See figure 5 4.5 V 25C 45 -40C to 125C 68 5.5 V 25C 40 -40C to
24、 125C 61 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04698 REV A PAGE 5 TABLE I. Electrical performance characteristics - Contin
25、ued. 1/ Test Symbol Conditions VCC Temperature, TA Device type Limits Unit Min Max Propagation delay time, output enable, OE to Y ten CL= 50 pF See figure 5 4.5 V 25C All 35 ns -40C to 125C 53 5.5 V 25C 32 -40C to 125C 48 CL= 150 pF See figure 5 4.5 V 25C 52 -40C to 125C 79 5.5 V 25C 47 -40C to 125C
26、 71 Propagation delay time, output disable, OE to Y tdis CL= 50 pF See figure 5 4.5 V 25C All 35 ns -40C to 125C 53 5.5 V 25C 32 -40C to 125C 48 Output transition time tt CL= 50 pF See figure 5 4.5 V 25C All 12 ns -40C to 125C 18 5.5 V 25C 11 -40C to 125C 16 CL= 150 pF See figure 5 4.5 V 25C 42 -40C
27、 to 125C 63 5.5 V 25C 38 -40C to 125C 57 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not nece
28、ssarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ The values to be used for VIHand VILshall be the VIHminimum and VILmaximum values listed in section 1.4 herein. 3/ This is the increase in supply current for each in
29、put that is at one of the specified TTL voltage levels, rather than 0.0 V or VCC. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04698 REV A PAGE 6 Case X Dimensi
30、ons Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.20 6.60 b 0.19 0.30 e 0.65 BSC c 0.15 NOM L 0.50 0.75 D 6.40 6.60 NOTES: 1. All linear dimensions are in millimeters. 2. This case outline is subject to change without notice. 3. Body dimensions do not inc
31、lude mold flash or protrusion, not to exceed 0.15 millimeters. 4. Fall within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62
32、/04698 REV A PAGE 7 Each buffer/driver Inputs Output OE A Y L H H L L L H X Z H = High voltage level Z = High impedance L = Low voltage level X = Dont care FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outlines: X and Y Terminal number Terminal symbol Terminal number Terminal s
33、ymbol 1 1 OE 11 2A1 2 1A1 12 1Y4 3 2Y4 13 2A24 1A2 14 1Y3 5 2Y3 15 2A36 1A3 16 1Y2 7 2Y2 17 2A48 1A4 18 1Y1 9 2Y1 192 OE 10 GND 20 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLU
34、MBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04698 REV A PAGE 8 NOTES: 1. CLincludes probe and test-fixture capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal con
35、ditions such that the output is high except when disabled by the output control. 3. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 , tr= 6 ns, tf= 6 ns. 4. The outputs are measured one
36、 at a time with one input transition per measurement. 5. tPLZand tPHZare the same as tdis; tPZLand tPZHare the same as ten; tPLHand tPHLare the same as tpd. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
37、DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04698 REV A PAGE 9 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedu
38、res should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standar
39、d commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers
40、data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued ava
41、ilability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04698-01XE 01295 SN74HCT244QPWREP SHT244EP 1/ The vendor item drawing establishes an administrative control number for identifying
42、the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
