1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Activate device type 03. - CFS 07-02-21 Thomas M. Hess B Correct package style in 1.2.2. - CFS 07-04-17 Thomas M. Hess C Update boilerplate to current MIL-PRF-38535 requirements. - PHN 13-12-11 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHAN
2、GED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV C C C C C C C C C C C C C C C C C C C C C PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 REV STATUS OF PAGES REV C C C C C C C C C C C C C C C C
3、 C PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL SIGNAL PROCESSORS, MONOLITHIC SILICON YY MM DD 06-05-09 APPROVED BY Thomas M. H
4、ess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06619 REV C PAGE 1 OF 38 AMSC N/A 5962-V022-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06619 REV C PAGE 2 1. S
5、COPE 1.1 Scope. This drawing documents the general requirements of a high performance floating-point digital signal processor microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification
6、. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06619 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 0
7、1 SM320F2808-EP Digital Signal Processors 02 SM320F2806-EP Digital Signal Processors 03 SM320F2801-EP Digital Signal Processors 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 100 JEDEC MS-026 Plastic quad flatpack 1.2.3 Le
8、ad finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1/ Users are cautioned to review the manufacturers data manual for
9、 additional user information relating to this device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06619 REV C PAGE 3 1.3 Absolute maximum ratings. 2/ 3/ Supply
10、 voltage ranges, (VDDIO, VDD3VFL) (with respect to VSS) -0.3 V to +4.6 V Supply voltage ranges, (VDDA2, VDDAIO) (with respect to VSSA) -0.3 V to +4.6 V Supply voltage ranges, (VDD) (with respect to VSS) . -0.3 V to +2.5 V Supply voltage ranges, (VDD1A18, VDD2A18) (with respect to VSSA) -0.3 V to +2.
11、5 V Supply voltage ranges, (VSSA2, VSSAIO, VSS1AGND, VSS2AGND) (with respect to VSS) -0.3 V to +0.3 V Input voltage range, (VIN) . -0.3 V to +4.6 V Output voltage range, (VO) . -0.3 V to +4.6 V Input clamp current, IIK(VINVDDIO) . 20 mA 4/ Output clamp current, IOK(VOVDDIO) 20 mA Operating ambient t
12、emperature ranges, (TA) -55C to +125C 5/ Junction temperature range TJ. -55C to +150C 5/ Storage temperature range, (TSTG) -65C to +150C 5/ 1.4 Recommended operating conditions. Device supply voltage, I/O, (VDDIO) . +3.14 V to +3.47 V Device supply voltage, CPU (VDD) +1.71 V to 1.89 V Supply ground,
13、 (VSS, VSSIO) 0 V ADC supply voltage, 3.3 V (VDDA2, VDDAIO) . +3.14 V to +3.47 V ADC supply voltage, 1.8 V (VDD1A18, VDD2A18) . +1.71 V to +1.89 V Flash programming supply voltage, (VDD3VFL) . +3.14 V to +3.47 V Device clock frequency (system clock), (fSYSCLKOUT) . 2 MHz to 100 MHz High level input
14、voltage, (VIH) . +2.0 V to VDDIOMaximum low level input voltage, (VIL) . 0.8 V Maximum high level output source current, VOH= 2.4 V (IOH) : All I/Os except group 2 . -4 mA Group 2 6/ . -8 mA Maximum low level output sink current, VOL= VOLmax (IOL) : All I/Os except group 2 . 4 mA Group 2 6/ . 8 mA A
15、mbient temperature, (TA) -55C to +125C Thermal resistance characteristics for case outline X: Parameter Air Flow 0 lfm 150 lfm 250 lfm 500lfm JAC/W High k PCB 48.16 40.06 37.96 35.17 JTC/W 0.3425 0.85 1.0575 1.410 JC12.89 JB29.58 2/ Stresses beyond those listed under “absolute maximum rating” may ca
16、use permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect dev
17、ice reliability. 3/ All voltage values are with respect to VSS, unless otherwise noted. 4/ Continuous clamp current per pin is 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the voltage to a diode drop above VDDA2or below VSSA25/ Long term high temperature
18、storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. 6/ Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLOUT, EMU0, and EMU1. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
19、-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06619 REV C PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at ht
20、tp:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers nam
21、e, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and ele
22、ctrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figur
23、e 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.5 Package life time versus operating junction temperature. The package life time versus operating junction temperature shall be as sp
24、ecified in figure 4. 3.5.6 Typical operational power versus frequency (for device type 01). The typical operational power versus frequency (for device type 01) shall be as specified in figure 5. 3.5.7 Test load circuits. The test load circuits shall be as specified in figure 6. 3.5.8 Timing waveform
25、s. The timing waveforms shall be as shown in figures 7- 27. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06619 REV C PAGE 5 TABLE I. Electrical performance char
26、acteristics. 1/ Test Symbol Test condition 2/ Limits Unit Min Max High level output voltage VOHIOH= IOH max2.4 V IOH= 50 A VDDIO 0.2 Low level output voltage VOLIOL = IOL max0.4 V Low level input current With pull up IILVDDIO= 3.3 V, VIN= 0 V All I/Os (including XRS ) -80 -190 A Pull up disabled VDD
27、IO= 3.3 V, VIN= 0 V 2 High level input current With pull up IIHVDDIO= 3.3 V, VIN= VDD2 A Pull up disabled 38 80 Off state output current, high impedance state (off state) IOZVO= VDDIOor 0 V 2 A Input capacitance Ci2 Typ pF Current consumption by power supply pins at 100 MHz SYSCLOUT - Device type 01
28、 Mode Test condition IDDIDDIO3/ IDD3VFL IDDA184/ IDDA335/ Typ 6/ Max Typ 6/ Max Typ Max Typ 6/ Max Typ 6/ Max Operational (Flash) 7/ 195 mA 230 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA IDLE 8/ 75 mA 90 mA 500 A 2 mA 2 A 10 A 5 A 50 A 15 A 30 A SWTANDBY 9/ 6 mA 12 mA 100 A 500 A 2 A 10 A 5
29、A 50 A 15 A 30 A HALT 10/ 70 A 60 A 120 A 2 A 10 A 5 A 50 A 15 A 30 A Current consumption by power supply pins at 100 MHz SYSCLOUT - Device type 02 Operational (Flash) 7/ 195 mA 230 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA IDLE 8/ 75 mA 90 mA 500 A 2 mA 2 A 10 A 5 A 50 A 15 A 30 A SWTANDBY
30、 9/ 6 mA 12 mA 100 A 500 A 2 A 10 A 5 A 50 A 15 A 30 A HALT 10/ 70 A 60 A 120 A 2 A 10 A 5 A 50 A 15 A 30 A Current consumption by power supply pins at 100 MHz SYSCLOUT - Device type 03 Operational (Flash) 11/ 180 mA 210 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA IDLE 8/ 75 mA 90 mA 500 A 2
31、mA 2 A 10 A 5 A 50 A 15 A 30 A SWTANDBY 9/ 6 mA 12 mA 100 A 500 A 2 A 10 A 5 A 50 A 15 A 30 A HALT 10/ 70 A 60 A 120 A 2 A 10 A 5 A 50 A 15 A 30 A See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUM
32、BUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06619 REV C PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ No Test Symbol Test condition 2/ Limits Unit Min Max Clock table and Nonmenclature On-chip oscillator clock tc(OSC), Cycle time 28.6 50 ns Frequency 20 35 MHz
33、 XCLKIN 12/ tc(CI), Cycle time 10 250 ns Frequency 4 100 MHz SYSCLKOUT tc(SCO), Cycle time 10 500 ns Frequency 2 100 MHz XCLKOUT tc(XCO), Cycle time 10 2000 ns Frequency 0.5 100 MHz HSPCLK 13/ tc(HCO), Cycle time 10 ns Frequency 100 MHz LSPCLK 13/ tc(LCO), Cycle time 10 ns Frequency 100 MHz ADC cloc
34、k tc(ADCCLK), Cycle time 80 ns Frequency 12.5 MHz Input clock frequency Input clock frequency fxResonator 20 35 MHz Crystal 20 35 External oscillator/clock Source (XCLKIN or X1 pin) Without PLL 4 100 With PLL 5 30 Limp mode clock frequency fl1-5 Typ XCLKIN 14/ timing requirements PLL Enabled C8 Cycl
35、e time, XCLKIN tc(CI)See figure 7 33.3 200 ns C9 Fall time, XCLKIN tf(CI)6 C10 Rise time, XCLKIN tr(CI)6 C11 Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)tw(CIL)45 55 % C12 Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)tw(CIH)45 55 See notes at end of table. Provided by IHSNot
36、for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06619 REV C PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ No Test Symbol Test condition 2/ Limits Unit Min Ma
37、x XCLKIN 14/ timing requirements PLL disabled C8 Cycle time, XCLKIN tc(CI)See figure 7 10 250 ns C9 Fall time, XCLKIN tf(CI)Up to 20 MHz 6 20 MHz to 100 MHz 2 C10 Rise time, XCLKIN tr(CI)Up to 20 MHz 6 20 MHz to 100 MHz 2 C11 Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)tw(CIL)XCLKIN 120
38、MHz 45 55 % C12 Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)tw(CIH)XCLKIN 120 MHz 45 55 XCLKOUT Switching characteristics (PLL Bypassed or Enabled) 15/ 16/ C1 Cycle time, XCLKOUT tc(XCO)See figure 7 10 ns C3 Fall time, XCLKOUT tf(XCO)2 Typ C4 Rise time, XCLKOUT tr(XCO)2 Typ C5 Pulse dur
39、ation, XCLKOUT low tw(XCOL)H-2 H+2 C6 Pulse duration, XCLKOUT high tw(XCOH)H-2 H+2 PLL lock time tp131072tc(OSCCLK) 17/ cycles Reset ( XRS ) timing requirements Pulse duration, stable XCLKIN to XRS high tw(RSL1) 18/ See figure 8-10 8tc(OSCCLK)cycles Pulse duration, XRS low tw(RSL2)Warm reset 8tc(OSC
40、CLK)Pulse duration, reset pulse generated by watchdog tw(WDRS)512tc(OSCCLK) Typ Delay time, address/data valid after XRS high td(EX)32tc(OSCCLK) Typ Oscillator start-up time tOSCT 19/ 1 10 ms Hold time for boot mode pins th(boot-mode)200tc(OSCCLK) cycles See notes at end of table. Provided by IHSNot
41、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06619 REV C PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition 2/ Limits Unit Min Max
42、GENERAL PURPOSE INPUT/OUTPUT (GPIO) General purpose output switching characteristics (See figure 11) Rise time, GPIO switching low to high tr(GPO)All GPIOs 8 ns Fall time, GPIO switching high to low tf(GPO)All GPIOs 8 Toggling frequency, GPO pins fGPO25 MHz General purpose input timing requirements
43、(See figure 12-13) Sampling period tw(SP)QUALPDR = 0 2*tc(SCO)cycles QUALPDR 0 2*tc(SCO)*QUALPRD Input qualifier sampling window tw(IQSW) tw(SP)*(n20/ -1) Pulse duration, GPIO low/high tr(GPI) 21/ Synchronous mode 2*tc(SCO)With input qualifier tw(IQSW)+ tw(SP)+1tc(SCO)LOW POWER MODE WAKEUP TIMING ID
44、LE mode timing requirements 22/ (See figure 14) Pulse duration, external wake up signal tw(WAKE-INT)Without input qualifier 2tc(SCO)cycles With input qualifier 5tc(SCO) + tw(IQSWIDLE mode switching characteristics 22/ Delay time, external wake signal to program execution resume 11/ td(WAKE-IDLE)- Wa
45、ke up from Flash - Flash module in active state Without input qualifier 20tc(SCO)cycles With input qualifier 20tc(SCO) + tw(IQSW)- Wake up from Flash - Flash module in sleep state Without input qualifier 1050tc(SCO)cycles With input qualifier 1050tc(SCO)+tw(IQSW)- Wake up from SARAM Without input qu
46、alifier 20tc(SCO)cycles With input qualifier 20tc(SCO)+tw(IQSW)STANDBY mode timing requirements (See figure 15) Pulse duration, external wake up signal tw(WAKE-INT)Without input qualification 3tc(OSCCLK)cycles With input qualification 24/ (2+QUALSTDBY)* tc(OSCCLK)STANDBY mode switching characteristi
47、cs (See figure 15) Delay time, IDLE instruction executed to XCLKOUT low td(IDLE-XCOL)32tc(SCO)45tc(SCO)cycles Delay time, external wake signal to program execution resume 23/ - Wake up from Flash - Flash module in active state td(WAKE-STBY)Without input qualifier 100tc(SCO)With input qualifier 100tc
48、(SCO)+tw(WAKE-INT)- Wake up from Flash - Flash module in sleep state Without input qualifier 1125tc(SCO)With input qualifier 1125tc(SCO)+tw(WAKE-INT)- Wake up from SARAM Without input qualifier 100tc(SCO)With input qualifier 100tc(SCO)+tw(WAKE-INT)See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-
