1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add top side marking in section 6.3.-phn 13-03-21 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITI
2、ME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, 200 MHz GENERAL PURPOSE CLOCK BUFFER, PCI-X COMPLIANT, MONOLITHIC SILICON 12-04-24 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V
3、62/12618 REV A PAGE 1 OF 12 AMSC N/A 5962-V056-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12618 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general req
4、uirements of a high performance 200 MHz general purpose clock buffer, PCI-X compliant microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an
5、 administrative control number for identifying the item on the engineering documentation: V62/12618 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 CDCV304-EP 200 MHz general purpose clock
6、buffer, PCI-X compliant 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 8 JEDEC MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device man
7、ufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V
8、62/12618 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VDD) . -0.5 V to 4.3 V Input voltage range, (VI) . -0.5 V to VDD+ 0.5 V 2/ 3/ Output voltage range, (VO) . -0.5 V to VDD+ 0.5 V 2/ 3/ Input clamp current, (IIK) (VIVDD) . 50 mA Output clamp current, (IOK) (VOVDD) . 50 mA Con
9、tinuous total output current, (IO) (VO= 0 to VDD) 50 mA Storage temperature range (Tstg) -65C to 150C Thermal information 4/ Case X Unit Junction to ambient thermal resistance (JA) 5/ 157.8 C/W Junction to case (top) thermal resistance (JA) 6/ 61.8 Junction to board thermal resistance (JA) 7/ 104.3
10、Junction to top characterization parameter (JT) 8/ 7.7 Junction to board characterization parameter (JB) 9/ 102.6 1.3 Recommended operating conditions. Supply voltage, (VDD) . 2.3 V to 3.6 V Low level input voltage, (VIL) 0.3 x VDDV maximum High level input voltage, (VIH) . 0.7 x VDDV minimum High l
11、evel output current, (IOH): VDD= 2.5 V -12 mA maximum VDD= 3.3 V -24 mA maximum Low level output current, (IOL): VDD= 2.5 V 12 mA maximum VDD= 3.3 V 24 mA maximum Operating free air temperature, (TA) . -55C to 125C Clock frequency (fclk) 0 to 200 MHz 1/ Stresses beyond those listed under “absolute m
12、aximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended
13、periods may affect device reliability. 2/ The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 3/ This value is limited to 4.6 V maximum. 4/ For more information about tradition and new thermal metrics, see manufacturer data. 5/ Th
14、e junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC standard, high K board, as specified in JESD51-7, in an environment described in JESD51-2a. 6/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the pac
15、kage top. No specific JEDEC standard exists, but a close description can be found in the ANSI SEMI standard G30-88. 7/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 8/ The
16、Junction to top characterization parameter , JT, estimates the junction temperature of a device in a real system and in extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a. 9/ The Junction to board characterization parameter , JB, estimates the junction temp
17、erature of a device in a real system and in extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236
18、 DWG NO. V62/12618 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7 High Effective Therm
19、al Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Junction-to-board thermal resistance Theta-JB or RJB. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201
20、.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be mark
21、ed with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dim
22、ension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The funct
23、ional block diagram shall be as shown in figure 3. 3.5.4 Terminal function. The terminal function shall be as shown in figure 4. 3.5.5 Test load circuit. The test load circuit shall be as shown in figure 5. 3.5.6 Voltage waveforms propagation delay (tpd) measurements. The Voltage waveforms propagati
24、on delay (tpd) measurements shall be as shown in figure 6. 3.5.7 Output skew. The output skew shall be as shown in figure 7. 3.5.8 Clock waveform. The clock waveform shall be as shown in figure 8. 3.5.9 Supply current vs frequency. The supply current vs frequency shall be as shown in figure 9. 3.5.1
25、0 High level output voltage vs high level output current. The high level output voltage vs high level output current shall be as shown in figure 10. 3.5.11 Low level output voltage vs low level output current. The low level output voltage vs low level output current shall be as shown in figure 11. P
26、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12618 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Input volta
27、ge VIKVDD= 3 V, II= -18 mA -1.2 V High level output voltage VOHVDD= 2.3 V, IOH= -8 mA 1.78 V VDD= min to max, IOH= -1 mA VDD 0.3 VDD= 3 V, IOH= -24 mA 1.9 VDD= 3 V, IOH= -12 mA 2.3 Low level output voltage VOHVDD= 2.3 V, IOL= 8 mA 0.51 V VDD= min to max, IOL= 1 mA 0.2 VDD= 3 V, IOL= 24 mA 0.84 VDD=
28、3 V, IOL= 12 mA 0.60 High level output current IOHVDD= 3 V, VO= 1 V -45 mA VDD= 3.3 V, VO= 1.65 V -55 TYP Low level output current IOLVDD= 3 V, VO= 2 V 54 VDD= 3.3 V, VO= 1.65 V 70 TYP Input current IIVI= VOor VDD5 A Dynamic current, See Figure 9. IDDf = 67 MHz, VDD= 2.7 V 28 mA f = 67 MHz, VDD= 3.6
29、 V 37 Input capacitance CIVDD= 3.3 V, VO= 0 V or VDD3 TYP pF Output capacitance COVDD= 3.3 V, VO= 0 V or VDD3.2 TYP See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT N
30、O. 16236 DWG NO. V62/12618 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Limits Unit Min Max Switching characteristics for VDD= 2.5 V 10%, CL= 10 pF (unless otherwise noted) Low to high propagation delay tPLHSee figure 2 4.5 ns High to low propaga
31、tion delay tPHL2 4.5 Output skew 3/ tsk(o)See figure 150 ps Output rise slew rate tr1 4 V/ns Output fall slew rate tf1 4 Switching characteristics for VDD= 3.310%, CL= 10 pF (unless otherwise noted) Low to high propagation delay tPLHSee figure 1.8 3.8 ns High to low propagation delay tPHL1.8 3.8 Out
32、put skew 3/ tsk(o)See figure 100 ps Additive phase jitter from input to output 1Y0 tjitter12 kHz to 5 MHz, fout= 30.72 MHz 63 TYP fs rms 12 kHz to 20 MHz, fout= 125 MHz 56 TYP Pulse skew tsk(p)180 TYP ps Process skew tsk(pr)0.2 TYP ns Part to part skew tsk(pp)0.25 TYP Clock high time, See figure 8.
33、thigh66 MHz 6 140 MHz 2.2 Clock low time, See figure 8. tlow66 MHz 6 140 MHz 3 Output rise slew rate 4/ trVO= 0.4 V to 2 V 1.5 4 V/ns Output rise fall rate 4/ tfVO= 2 V to 0.4 V 1.5 4 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performanc
34、e over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Over recommended opera
35、ting free air temperature range (unless otherwise noted). All typical values are with respect to nominal VDDand TA= 25C. 3/ The tsk(o) specification is only valid for equal loading of all outputs and TA= -40C to 85C 4/ This symbol is according to PCI-X terminology. Provided by IHSNot for ResaleNo re
36、production or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12618 REV PAGE 7 Case X SEATINGPLANESEEDETAIL AbD1 458E E1AA1e0.25c0-8LDETAIL AGAGEPLANEM0.100.10Dimensions Symbol Millimeters Symbol Millimeters Min Max Min M
37、ax A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.20 6.60 b 0.19 0.30 e 0.65 BSC c 0.15 NOM L 0.50 0.75 D 2.90 3.10 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, pro
38、trusion, or gate burrs shall not exceed 0.15 each side. 4. Body width does not include interlead flash. Interlead flash shall not exceed 0.25 each side 5. Falls within JEDEC MO-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-
39、,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12618 REV PAGE 8 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 CLKIN 5 1Y1 2 OE 6 VDD 3 1Y0 7 1Y2 4 GND 8 1Y3 FIGURE 2. Terminal connections. LOGICCONTROLOECLKIN 1Y01Y11Y21Y3FIGURE 3.
40、Functional block diagram. Terminal I/O Description Name No. 1Y0:3 3, 5, 7, 8 O Buffered output clocks CLKIN 1 I Input reference frequency GND 4 Power Ground OE 2 I Output enable control VDD6 Power Supply FIGURE 4. Terminal function. Provided by IHSNot for ResaleNo reproduction or networking permitte
41、d without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12618 REV PAGE 9 140140YnVDD10 pFFIGURE 5. Test load circuit. CLKIN1Y0-1Y3DDV0 VDD50% VOHVDD50% VDD0.6 VDD0.2 VOLVPLHtPHLtrtftFIGURE 6. Voltage waveforms propagation delay (tpd) measurements.
42、ANY YANY YDD50% VDD50% VtSK(0)FIGURE 7. Output skew Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12618 REV PAGE 10 HIGHtLOWtCYCtIH(MIN)VTESTVIL(MAX)VDD0.4 VPEAK TO PEAK(M
43、INIMUM)PARAMETER VALUE UNITIH(MIN)VTESTVIL(MAX)VDD0.5 VDD0.4 VDD0.35 VVVVDD0.6 VDD0.2 VNOTE: 1. All parameters in this figure are according to PCI-X 1.0 specifications. FIGURE 8. Clock waveform. 20304050600 20 40 60 80 100 120 140 160f-FREQUENCY-MHzOUTPUT LOAD:AS IN FIGURE 1TA=85CVDD=3.6 VVDD=2.7 VC
44、CI-SUPPLY CURRENT-mAFIGURE 9. Supply current vs Frquency. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12618 REV PAGE 11 0.00.51.01.52.02.53.03.5-100 -90 -80 -70 -60 -50
45、-40 -30 -20 -10 0-HIGH-LEVEL OUTPUT CURRENT-mAIOH-HIGH-LEVEL OUTPUT VOLTAGE-VVOHDDV =3.3 VAT =25CFIGURE 10. High level output voltage vs high level output current. 0.00.51.01.52.02.53.03.5-20 0 20 40 60 80 100 120-LOW-LEVEL OUTPUT CURRENT-mAIOL-LOW-LEVEL OUTPUT VOLTAGE-VVOLDDV =3.3 VAT =25CFIGURE 11
46、. Low level output voltage vs low level output current. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12618 REV A PAGE 12 4. VERIFICATION 4.1 Product assurance requirement
47、s. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and ar
