1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Inactivate device type 01 for new design. Use M38510/12101BJX. 84-03-14 N. A. Hauck B Redraw. Update drawing to current requirements. - drw 08-06-03 Robert M. Heber THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE 672
2、68 REV SHET REV SHET REV STATUS REV B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY W. E. Shoup CHECKED BY C. R. Jackson DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY N. A. Hauck STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS
3、 AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 82-10-13 MICROCIRCUIT, LINEAR, MONOLITHIC AND MULTICHIP, 12-BIT DIGITAL-TO-ANALOG CONVERTERS AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 14933 81008 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E407-08 P
4、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81008 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requir
5、ements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 81008 01 J A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see
6、 1.2.3)1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 562 D/A converter, 12-bit, external reference, 2 mA FS. 02 563 D/A converter, 12-bit, internal reference, 2 mA FS. 1.2.2 Case outline. The case outline is as designate
7、d in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltages (VS) . 18 V Reference voltage, HI input
8、VSReference voltage, LO input . VSDigital inputs . VSCMOS/TTL logic select. VSOutput pins 7, 8, 10, 11 VSOutput pin 9 VS-5 Lead temperature (soldering, 60 seconds) . 300C Junction temperature (TJ) . 175C Storage temperature. -65C to +150C Power dissipation (PD) 1W, TA= +125C 1.4 Recommended operatin
9、g conditions. Supply voltage range Device type 01 VCC= 4.5 V to 16.5 V, VEE= -15 V 1.5 V Device type 02 VCC= 4.75 V to 15.8 V, VEE= -15 V 0.75 V Reference voltage (device type 01) 10.000 V Output compliance voltage . 0 V Logic thresholds: TTL Logic “0”. 0.8 V Logic “1”. 2.0 V CMOS Logic “0” 30% VCCL
10、ogic “1” 70% VCCAmbient temperature range (TA). -55C to +125C Thermal resistance, junction-to-case (JC) 15C/W, TA= +125C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81008 DEFENSE SUPPLY CENTER COLUMBUS COLUMBU
11、S, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues o
12、f these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard El
13、ectronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order
14、 Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and reg
15、ulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81008 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97
16、 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified m
17、anufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Mana
18、gement (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify
19、when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connecti
20、ons. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical tes
21、t requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In a
22、ddition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be mark
23、ed on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance
24、shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-
25、PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be
26、required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the revi
27、ewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81008 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics.
28、Test Symbol Conditions 1/, 2/, 3/ -55C TA +125C VCC= 5.0 V, VEE= -15.0 V, VREF= 10.000 V, Logic “0” = 0.8 V, Logic “1” = 2.0 V Group A subgroupsDevice type Limits Unit unless otherwise specified Min Max Monotonicity Guaranteed by the bit linearity and major carry error tests All 12 Bits Supply curre
29、nt from VCCICCVCC= 15 V, All input bits = 10.5 V 1, 2, 3 01 3 18 mA 02 3 20 Supply current from VEEIEEVCC= 15 V, All input bits = 4.5 V 1, 2, 3 All -25 -5 mA Logic “1” input current IIHVCC= 15 V, VIN(logic “1”) = 10.5 V Each input measured separately 1, 2, 3 All -1 +100 A Logic “0” input current IIL
30、VCC= 15 V, VIN(logic “0”) = 0 V Each input measured separately 1, 2, 3 All -200 +1 A Full scale current IFSAll inputs logic “1”, VO= 0 V 1, 2, 3 All -2.7 -1.6 mA Zero scale current (TTL) IZS1All inputs logic “0”, VO= 0 V, TA= 25C 1 All -0.05 +0.05 %IFS Zero scale current (CMOS) IZS2All inputs bits =
31、 4.5 V, VO= 0 V, VCC= 15 V, TA= 25C 1 All -0.05 +0.05 %IFS Zero scale current drift IZ5T All inputs logic “0” 2, 3 All -2 2 PPMIFS /C Gain error (TTL) AE11 01 -0.20 +0.20 % Zero scale to full scale, AE1= 10 (VFS VOS 9.99756), TA= 25C 2/ 02 -0.16 +0.16 Gain error (CMOS) AE21 01 -0.20 +0.20 % All inpu
32、t bits = 10.5 V, AE2= 10 (VFS VOS 9.99756), VCC= 15 V, TA= 25C 2/ 02 -0.16 +0.16 Bipolar gain error AE31 01 -0.20 +0.20 % -Full scale to +full scale, AE3= 5 (VFS BPO 19.99512), TA= 25C 2/ 02 -0.16 +0.16 Gain drift AET All inputs logic “1” 2, 3 01 -5 +5 PPM/C 02 -30 +30 See footnotes at end of table.
33、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81008 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - cont
34、inued. Test Symbol Conditions 1/, 2/, 3/ -55C TA +125C VCC= 5.0 V, VEE= -15.0 V, VREF= 10.000 V, Logic “0” = 0.8 V, Logic “1” = 2.0 V Group A subgroupsDevice type Limits Unit unless otherwise specified Min Max Bipolar offset error BPOEAll inputs logic “0”, TA= 25C, BPOE= 5 (VOUT+ 10.000) 1 01 -0.20
35、+0.20 %VFSRBipolar offset drift BPOET All inputs logic “0”, measure VO2, 3 01 -4 +4 PPMVFSR/C Bipolar zero error (TTL) BZEInput bits = 4000 (octal), TA= 25C, BZE= 5 (VOUT) 1 02 -0.16 +0.16 % Bipolar zero drift BZET Input bits 4000 (octal) 2, 3 02 -10 +10 PPMVFSR/C Power supply sensitivity from VCCat
36、 full scale +PSS1VCC= 5 V 0.5 V, TA= +25C 1 01 -0.8 0.8 mV (TTL) 02 -3.2 3.2 VCC= 5 V 0.5 V, -55C TA +125C 1, 2, 3 01 -1.6 1.6 02 -6.4 6.4 Power supply sensitivity from VCCat full scale +PSS2VCC= 15 V 1.5 V, TA= +25C 1 01 -0.8 0.8 mV (CMOS) 02 -3.2 3.2 VCC= 15 V 1.5 V, -55C TA +125C 1, 2, 3 01 -1.6
37、1.6 02 -6.4 6.4 Power supply sensitivity from VEEat full scale -PSS1VEE= 15 V 1.5 V, TA= +25C 1 01 -1.6 1.6 mV 02 -6.4 6.4 VEE= 15 V 1.5 V, -55C TA +125C 1, 2, 3 01 -3.2 3.2 02 -12.8 12.8 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without lice
38、nse from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81008 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/, 2/, 3/ -55C TA +125C VCC= 5.0 V, VEE= -15.0 V, V
39、REF= 10.000 V, Logic “0” = 0.8 V, Logic “1” = 2.0 V Group A subgroupsDevice type Limits Unit unless otherwise specified Min Max Bit linearity error LE 1, 2, 3 All -1.22 1.22 mV Major carry error (differential linearity) MCE The difference between adjacent codes at all major transitions (i.e. 0111 11
40、11 1111 to 1000 0000 0000) 1, 2, 3 All -1.0 1.0 LSB Output current settling time, 0 to FS tSLH9 All 3.0 s All inputs switched simultaneously. Measure the time to settle to within LSB of the final value. 10, 11 4.5 Output current settling time, FS to 0 tSHL9 All 3.0 s All inputs switched simultaneous
41、ly. Measure the time to settle to within LSB of the final value. 10, 11 4.5 Reference input impedance Zi VREF= 10 V, TA= 25C 9 All 15 25 k Output noise voltage NOVCC= 15 V, BW= 10 Hz to 100MHz, TA= 25C 9 01 62 VRMS02 100 1/ This test is performed in the unipolar mode over a 0 to 10 V range. One LSB
42、is 2.44 mV. 2/ VFSRis the full scale voltage range (all input bits = 1) minus (all input bits = 0). 3/ The output compliance voltage range may vary. Devices with a finite output resistance will draw additional current that is equal to the output compliance voltage divided by the device output resist
43、ance. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81008 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Device type 01 02 Case outline J Terminal number
44、Terminal symbol 1 VCC(+) VCC(+) 2 CMOS/TTL LOGIC THRESHOLD CMOS/TTL LOGIC THRESHOLD 3 REF V (-) REFERENCE IN SUPPLY 4 NC (see note) REFERENCE OUT (+2.5 V 3%) 5 REF V (+) REF GND 6 VEE(-) REFERENCE IN 7 BIPOLAR OFFSET R IN VEE(-) 8 BIPOLAR OFFSET R OUT BIPOLAR OFFSET IN 9 DAC OUT DAC OUT 10 10 V SPAN
45、 R 10 V SPAN R 11 20 V SPAN R 20 V SPAN R 12 GND GND 13 BIT 12 (LSB) BIT 12 (LSB) 14 BIT 11 BIT 11 15 BIT10 BIT10 16 BIT 9 BIT 9 17 BIT 8 BIT 8 18 BIT 7 BIT 7 19 BIT 6 BIT 6 20 BIT 5 BIT 5 21 BIT 4 BIT 4 22 BIT 3 BIT 3 23 BIT 2 BIT 2 24 BIT 1 (MSB) BIT 1 (MSB) NOTE: NC = Amplifier summing junction,
46、no external connection. FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 81008 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97
47、 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The
48、following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and powe
