1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added device types 03, 04, 05, and 06. Added electrical test limits for device types 03, 04, 05, and 06 to table I. Added vendor CAGE code 34335. Editorial changes throughout. 90-05-09 William K. Heckman B Added device types 07, 08, 09, and 10. A
2、dded electrical parameters testing to table I for device types 07, 08, 09, and 10. Added a new package for device type 07. Editorial changes throughout. 92-03-25 Monica L. Poelking C Added vendor CAGE code 0C7V7. Update boilerplate to MIL-PRF-38535 requirements. LTG 02-12-18 Thomas M. Hess D Update
3、boilerplate to current MIL-PRF-38535 requirements. CFS 07-12-05 Thomas M. Hess E Update boilerplate to current MIL-PRF-38535 requirements. - PHN 13-06-06 Thomas M. Hess REV SHEET REV E E E E E E E E E E E E E E E SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 REV STATUS REV E E E E E E E E E E E
4、 E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Tim H. Noh DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Tim H. Noh THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY William K. He
5、ckman MICROCIRCUIT, DIGITAL, CMOS, SERIAL COMMUNICATION CONTROLLER, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-02-06 MONOLITHIC SILICON AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-88689 SHEET 1 OF 29 DSCC FORM 2233 APR 97 5962-E443-13 Provided by IHSNot for ResaleNo
6、 reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88689 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant,
7、non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88689 01 Q X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s
8、). The device type(s) identify the circuit function as follows: Device type Generic number Frequency Circuit function 01 Z85C3006 6.0 MHz Serial communication controller 02 Z85C3008 8.0 MHz Serial communication controller 1/ 03 AM85C30-10 10.0 MHz Serial communication controller with SDLC enhancemen
9、ts 2/ 04 AM85C30-12 12.0 MHz Serial communication controller with SDLC enhancements 05 AM85C30-16 16.0 MHz Serial communication controller with SDLC enhancements 2/ 06 AM85C30-08 8.0 MHz Serial communication controller with SDLC enhancements 2/ 07 Z85C3010 10.0 MHz Serial communication controller 3/
10、 08 Z8523010 10.0 MHz Serial communication controller with SDLC enhancements 2/ 09 Z8523016 16.0 MHz Serial communication controller with SDLC enhancements 2/ 10 Z8523008 8.0 MHz Serial communication controller with SDLC enhancements 2/ 1.2.2 Case outline(s). The case outline(s) are as designated in
11、 MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 Dual-in-line X GQCC1-J44 44 “J” lead chip carrier Y CQCC1-N44 44 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. _ 1/
12、Device type 02 is not functionally identical with device types 06 or 10. 2/ Device types 03, 05, 06, 08, 09, and 10 are not functionally identical. 3/ Device type 07 is not functionally identical with device types 03 or 08. Provided by IHSNot for ResaleNo reproduction or networking permitted without
13、 license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88689 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. VCCsupply voltage range (referenced to ground) -0.3 V dc to +7.0 V dc Voltage on any pin (referenced to g
14、round) -0.3 V dc to +7.0 V dc Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) . 0.5 W Lead temperature (soldering, 10 seconds) +270C Maximum operating junction temperature (TJ) . +180C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 1.4 Recommended operat
15、ing conditions. Supply voltage (VCC) 4.5 V dc minimum to 5.5 V dc maximum Minimum high level input voltage (VIH) . 2.2 V dc Maximum low level input voltage (VIL) . 0.8 V dc Frequency of operation: Device type 01 . 0.5 MHz to 6.0 MHz Device types 02, 06, 10 0.5 MHz to 8.0 MHz Device types 03, 07, 08
16、0.5 MHz to 10 MHz Device type 04 . 0.5 MHz to 12.5 MHz Device types 05 and 09 0.5 MHz to 16.4 MHz Case operating temperature range (TC) . -55C to +125C Clock rise and fall times: Device type 09 . 5 ns maximum Device type 05 . 8 ns maximum Device types 01, 02, 03, 04, 06, 07, 08, 10 10 ns maximum 2.
17、APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DE
18、PARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL
19、-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094).
20、 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by I
21、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88689 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements
22、shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certifica
23、tion to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These
24、 modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical
25、dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.
26、2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Timing waveforms and test circuits. The timing waveforms and test circuits shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance charac
27、teristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking
28、 shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option
29、 of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with
30、 MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 and QML-38535 (see 6.6 herein). The certificate of compliance submitted
31、to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, append
32、ix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s age
33、nt, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
34、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88689 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C VCC= 5.0 V 10% unless otherwise specified Group A subgroups
35、 Device type Limits Unit Min Max High input voltage VIH1, 2, 3 All 2.2 VCC+0.3 2/ V Low input voltage VIL1, 2, 3 All -0.3 2/ 0.8 V Logic low output voltage VOLIOL= 2.0 mA, VCC= 4.5 V 1, 2, 3 All 0.5 V Logic high output voltage VOH1IOH= -1.6 mA, VCC= 4.5 V 1, 2, 3 All 2.4 V VOH2IOH= -250 A, VCC= 4.5
36、V 1, 2, 3 All VCC-0.8 V Power supply current ICC VIH= 4.8 V VIL= 0.2 V VCC= 5.0 V Oscillator off 1, 2, 3 01,02,06 30 mA 1, 2, 3 03,07,08 18 1, 2, 3 04,05,09 22 1, 2, 3 10 15 Output leakage current low ILOLVOUT= 0.4 V, VCC= 5.5 V 1, 2, 3 All -10 A Output leakage current high ILOHVOUT= 2.4 V, VCC= 5.5
37、 V 1, 2, 3 All +10 Input low current IILVIN= 0.4 V, VCC= 5.5 V 1, 2, 3 All -10 Input high current IIHVIN= 2.4 V, VCC= 5.5 V 1, 2, 3 All +10 Input capacitance CINfc = 1.0 MHz See 4.3.1c 4 All 10 pF Output capacitance COUT4 All 15 Bidirectional capacitance CI/O4 All 20 Functional test See 4.3.1d VCC=
38、4.5 V, 5.5 V 7, 8 All Maximum frequency fMAXSee figure 3 VCC= 4.5 V 9, 10, 11 05, 09 16.0 MHz 04 12.0 03,07,08 10.0 02,06,10 8.0 01 6.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE
39、A 5962-88689 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC +125C VCC= 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits Unit M
40、in Max PCLK low width twPCLSee figure 3, read and write, interrupt, reset, and cycle timings. CL= 50 pF 10% VCC= 4.5 V 9, 10, 11 1 01 70 1000 ns 02,06,10 50 1000 03,07,08 40 1000 04 34 1000 05, 09 26 1000 PCLK high width twPCH9, 10, 11 2 01 70 1000 ns 02,06,10 50 1000 03,07,08 40 1000 04 34 1000 05,
41、 09 26 1000 PCLK fall time 2/ 3/ tfPC9, 10, 11 3 01,02,03, 04,06,07, 08, 10 10 ns 05 8 09 5 PCLK rise time 2/ 3/ trPC9, 10, 11 4 01,02,03, 04,06,07, 08, 10 10 ns 05 8 09 5 PCLK cycle time tcPC9, 10, 11 5 01 165 2000 ns 02,06,10 125 2000 03,07,08 100 2000 04 80 2000 05, 09 61 2000 Address to WR setup
42、 time tsA(WR) 9, 10, 11 6 01 80 ns 02,06,10 70 03,07,08 50 04 45 05, 09 35 Address to WR hold time thA(WR) 9, 10, 11 7 All 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-8
43、8689 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC +125C VCC= 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits Unit Min Max A
44、ddress to RD setup time tsA(RD) See figure 3, read and write, interrupt, reset, and cycle timings. CL= 50 pF 10% VCC= 4.5 V 9, 10, 11 8 01 80 ns 02,06,10 70 03,07,08 50 04 45 05, 09 35 Address to RD hold time thA(RD) 9, 10, 11 9 All 0 ns INTACK to PCLK setup time 4/ tsIA(PC) 9, 10, 11 10 01,02,03, 0
45、6,07,08, 10 20 ns 04,05,09 15 INTACK to WR setup time 5/ tsIAi(WR) 9, 10, 11 11 01 160 ns 02,06,10 145 07 130 03, 08 120 04 95 05, 09 70 INTACK to WR hold time thIA(WR) 9, 10, 11 12 All 0 ns INTACK to RD setup time 5/ tsIAi(RD) 9, 10, 11 13 01 160 ns 02,03,06, 07,08,10 145 04 95 05, 09 70 INTACK to
46、RD hold time 4/ tsIAi(RD) 9, 10, 11 14 All 0 ns INTACK to PCLK hold time thIA(PC) 9, 10, 11 15 01 100 ns 02,06,10 40 03,07,08 30 04 20 05, 09 15 CE low to WR setup time tsCEL(WR) 9, 10, 11 16 All 0 ns CE to WR hold time thCE(WR) 9, 10, 11 17 All 0 ns See footnotes at end of table. Provided by IHSNot
47、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88689 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Condit
48、ions 1/ -55C TC +125C VCC= 5.0 V 10% unless otherwise specified Group A subgroups Ref no. Device type Limits Unit Min Max CE high to WR setup time tsCEh(WR) See figure 3, read and write, interrupt, reset, and cycle timings. CL= 50 pF 10% VCC= 4.5 V 9, 10, 11 18 01 70 ns 02,06,10 60 03,07,08 50 04 40 05, 09 30 CE low to RD setup time 5/ tsCEL(RD) 9, 10, 11 19 All 0 ns CE to RD hold time 5/ thCE(RD) 9, 10, 11 20 All 0 ns CE high to RD setup time 5/ tsCEh(RD) 9, 10, 11 21 01 70 ns 02,06,10 60 03,07,0
