1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Correct title to accurately describe the device function. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout. jak 06-11-08 Thomas M. Hess B Update boilerplate paragraphs to the current MIL-P
2、RF-38535 requirements. - LTG 13-03-25 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Wanda L. Meadows DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUI
3、T DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas J Ricciuti APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, 8-BIT ADDRESSABLE LATCH, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DA
4、TE 93-02-26 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89852 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E313-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89852 DLA LAND AND MARITIME COLUMBUS, OHIO 43218
5、-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the f
6、ollowing example: 5962-89852 01 E A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HCT259 8-bit addressable latch, TTL compatib
7、le inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute
8、maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc Input clamp current (IIK) (VINVCC + 0.5 V dc). 20 mA Output clamp current (IOK) (VOUTVCC + 0.5 V dc) . 20
9、 mA DC drain current (IOUT) (per output) (-0.5 V VOUT VCC + 0.5 V dc) . 25 mA DC VCCor GND current (ICC, IGND) 50 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) 500 mW 4/ Lead temperature (soldering, 10 seconds) . +265C Thermal resistance, junction-to-case (JC) See
10、MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Input voltage range (VIN) . 0.0 V dc to VCC Output voltage range (VOUT) 0.0 V dc to VCCCase operating temperature range (TC) -55C to +125C Input rise or fall
11、 time (tr, tf) (0.1VCCto 0.9VCC; 0.9VCCto 0.1VCC) 0 to 500 ns Maximum high level output current (IOH) . -4.0 mA Maximum low level output current (IOL) . +4.0 mA 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrad
12、e performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 8 mW/C to
13、300 mW. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89852 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specificatio
14、n, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535
15、- Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawin
16、gs. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Non-Government publications. The following docu
17、ment(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Spee
18、d CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201-2107). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the referenc
19、es cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535,
20、appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as Q
21、ML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit,
22、or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and p
23、hysical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as spec
24、ified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89852 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.2.4 Logic diagram. The logic diagram s
25、hall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in tabl
26、e I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-P
27、RF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the
28、 device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when th
29、e QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as
30、 an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcir
31、cuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option
32、to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 596
33、2-89852 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test and MIL-STD-883 test method Symbol Test conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Device type VCCGroup A subgroups Li
34、mits Unit Min Max High level output voltage 3006 VOH11/ For all inputs affecting output under test VIN= VIH= 2.0 V or VIL= 0.8 V For all other inputs VIN= VCCor GND IOH= -20 A All 4.5 V 1, 2, 3 4.4 V VOH21/ For all inputs affecting output under test VIN= VIH= 2.0 V or VIL= 0.8 V For all other inputs
35、 VIN= VCCor GND IOH= -4.0 mA All 5.5 V 1 3.98 2, 3 3.7 Low level output voltage 3007 VOL11/ For all inputs affecting output under test VIN= VIH= 2.0 V or VIL= 0.8 V For all other inputs VIN= VCCor GND IOL= +20 A All 4.5 V 1, 2, 3 0.1 V VOL21/ For all inputs affecting output under test VIN= VIH= 2.0
36、V or VIL= 0.8 V For all other inputs VIN= VCCor GND IOL= +4.0 mA All 5.5 V 1 0.26 2, 3 0.4 Input current low 3009 IILFor input under test VIN= GND For all other inputs VIN= VCCor GND All 5.5 V 1 -0.1 A 2, 3 -1.0 Input current high 3010 IIHFor input under test VIN= VCCFor all other inputs VIN= VCCor
37、GND All 5.5 V 1 0.1 A 2, 3 1.0 Quiescent supply current, output high 3005 ICCHFor all inputs, VIN= VCCor GND All 5.5 V 1 8 A 2, 3 160 Quiescent supply current, output low 3005 ICCLFor all inputs, VIN= VCCor GND All 5.5 V 1 8 A 2, 3 160 Additional quiescent supply current ICC2/ For input under test V
38、IN= 2.4 V For all other inputs VIN= VCCor GND All 5.5 V 1, 2, 3 3.0 mA Input capacitance 3012 CINVIN= 0.0 V, TC= +25C See 4.3.1c All GND 4 10 pF Power dissipation capacitance CPD3/ TC= +25C See 4.3.1c All 4 28 pF Functional tests 3014 See 4.3.1d All 7, 8 See footnotes at end of table. Provided by IH
39、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89852 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test and MIL-S
40、TD-883 test method Symbol Test conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Device type VCCGroup A subgroups Limits Unit Min Max LE pulse width tw12/ CL= 50 pF minimum See figure 4 All 4.5 V 9 18 ns 10, 11 27 MR pulse width tw22/ All 4.5 V 9 18 ns 10, 11 27 Setup time, D to LE
41、 ts12/ All 4.5 V 9 17 ns 10, 11 26 Setup time, An to LE ts22/ All 4.5 V 9 17 ns 10, 11 26 Hold time, D to LE th12/ All 4.5 V 9, 10, 11 0 ns Hold time, An to LE th22/ All 4.5 V 9, 10, 11 0 ns Propagation delay time, D to Qm 3003 tPLH1, tPHL1All 4.5 V 9 39 ns 10, 11 59 Propagation delay time, LE to Qm
42、 3003 tPLH2, tPHL2All 4.5 V 9 38 ns 10, 11 57 Propagation delay time, An to Qm 3003 tPLH3, tPHL3All 4.5 V 9 41 ns 10, 11 61 Propagation delay time, MR to Qm 3003 tPHL4All 4.5 V 9 39 ns 10, 11 59 Output transition time 3003 tTLH, tTHL 2/ All 4.5 V 9 15 ns 10, 11 22 1/ For power supply of 5 V 10 perce
43、nt, the worst case output voltages (VOHand VOL) occur for HCT at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. 2/ Guaranteed, if not tested, to the limits specified in table I. 3/ Power dissipation cap
44、acitance (CPD) determines the no load dynamic power consumption, PD= CPDVCC2f + (ICCx VCC) + n(ICCx VCCx d), and the no load dynamic current consumption, IS= CPDVCCf + ICC+ (n x d x ICC) Where: PD= dynamic power dissipation. CPD= power dissipation capacitance of the device. f = input switching frequ
45、ency. n = number of inputs switching. d = duty cycle. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89852 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Devic
46、e type 01 Case outlines E Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A0 A1 A2 Q0 Q1 Q2 Q3 GND Q4 Q5 Q6 Q7 D LE MR VCCTerminal symbol description Terminal symbol Description D Data input An (n = 0 to 2) Address select inputs Qm (m = 0 to 7) Outputs (non-inverting) MR Maste
47、r reset control input (active low) LE Latch enable control input (active low) FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89852 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3
48、990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Select inputs Latch addressed Inputs Output of addressed latch All other outputs Function A2 A1 A0 MR LE L L L 0 H L D Qio Addressable latch L L H 1 H H Qio Qio Memory L H L 2 L L D L 8-line demultiplexer L H H 3 L H L L Reset H L L 4 H L H 5 H H L 6 H H H 7 H = High voltage level L = Low voltage level D = Logic level at the data input Qio = Logic level of Qi (i = 0 to 7, as appropriate) before the indicated steady-state conditions were established FIGURE 2. Truth tables. Provided by IHSNot for Re
