1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated to current requirements lhl 12-08-24 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A A A A A A SHEET 15 16 17 18 19 20 21 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5
2、 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Jeff Bowling APPROVED B
3、Y Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS 128K X 8 BIT 5-VOLT PROGRAMMING EEPROM, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-08-05 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91682 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E423-12 Provided by IHSNot for ResaleNo reproduction or
4、 networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91682 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliabili
5、ty (device class Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as
6、 shown in the following example: 5962 - 91682 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked dev
7、ices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(
8、s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time Endurance 01 29C010 128K X 8 CMOS 5 V PROGRAMMING EEPROM 200 ns 1000 cycles 02 29C010 128K X 8 CMOS 5 V PROGRAMMING EEPROM 150 ns 1000 cycles 03 29C010 128K X 8 CMOS 5 V PROGRAMMI
9、NG EEPROM 120 ns 1000 cycles 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level
10、 B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T32 or CDIP2-T32 32
11、 Dual-in-line Y CQCC1-N32 32 Rectangular leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS
12、-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91682 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) 2/ . -0.5 V dc to +6.0 V dc Voltage on any pin with respect to ground 2/ -0.5 V dc to +6.0 V
13、 dc Voltage on pin A9 and OE with respect to ground 3/ . -0.5 V dc to +13.5 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) 1.0 W Lead temperature (soldering, 10 seconds) . +300C Junction temperature (TJ) . +150C 4/ Thermal resistance, junction-to-case (JC) . See MIL-STD-
14、1835 Data retention . 10 years minimum Endurance 1000 cycles/sector, minimum 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC) . -55C to +125C Low level input voltage range (VIL) . -0.5 V dc to +0.8 V dc High level input
15、voltage range (VIH1) . +2.0 V dc to VCC to +0.5 V dc High level input voltage range (VIH2) . VCC -0.5 V dc to VCC + 0.5 V dc Chip carrier voltage (VH) . +12.0 0.5 V dc 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbook
16、s form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DE
17、FENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are
18、 available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may
19、 degrade performance and affect reliability. 2/ Minimum dc voltage on input or VO pins is -0.5 V. During voltage transitions, inputs may overshoot VSS to -1.0 V for periods of up to 20 ns. Maximum dc voltage on output and VO pins is VCC +0.5 V. During voltage transitions outputs may overshoot to VCC
20、 +1.0 V for periods up to 20 ns. 3/ Maximum dc input voltage on A9 or OE may overshoot to +14.0 V for periods of less than 20 ns. 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 5/ A
21、ll voltages are referenced to VSS (ground). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91682 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Governm
22、ent publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Copies of
23、 this document are available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this dr
24、awing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specifi
25、ed herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN c
26、lass level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outli
27、ne(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table(s) shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation paramet
28、er limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the su
29、bgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due t
30、o space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance
31、with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML” or “Q” as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C” as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance.
32、For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an
33、approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-P
34、RF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot
35、 of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. Provided by
36、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91682 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.9 Verification and review for device class M. For device class M, DLA
37、 Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for devi
38、ce class M. Device class M devices covered by this drawing shall be in microcircuit group number 042 (see MIL-PRF-38535, appendix A). 3.11 Serialization of device class V. All class V devices shall be serialized in accordance to MIL-PRF-38535. 3.12 Processing of EEPROMs. All testing requirements and
39、 quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.12.1 Conditions of the supplied devices. Devices will be supplied in an unprogrammed or clear state. No provision will be made for supplying programmed devices. 3.12.2 Erasure of EEPROMs. When specified,
40、 devices shall be erased in accordance with procedures and characteristics specified in 4.5.2. 3.12.3 Programming of EEPROMs. When specified, devices shall be programmed in accordance with procedures and characteristics specified in 4.5.3. Software data protect shall be as specified in 4.5.4. 3.12.4
41、 Verification of state of EEPROMs. When specified, devices shall be verified as either written to the specified pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper state. Any bit that does not verify to be in
42、 the proper state shall constitute a device failure and device shall be removed from the lot or sample. 3.12.5 Power supply sequence of EEPROMs: In order to reduce the probability of inadvertent writes, the following power supply sequences shall be observed: a. A logic high state shall be applied to
43、 WE and/or CE at the same time or before the application of VCC. b. A logic high state shall be applied to WE and/or CE at the same time or before the removal of VCC. 3.13 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitors, this reprogrammability test
44、shall be done only for the initial characterization and after any design or process changes which may affect the reprogrammability of the device. This test shall consist of 1000 program/erase cycles on 25 devices with the following conditions: (1) All devices selected for testing shall be programmed
45、 per 3.12.3 herein (see 4.5.4). (2) Verify pattern (see 3.12.4). (3) Erase (see 3.12.2). (4) Verify pattern erasure (see 3.12.4). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91682 DLA LAND AND MARITIME CO
46、LUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 1/ 4.5 V VCC 5.5 V Group A subgroups Device type Limits Units unless otherwise specified Min Max Input leakage current ILI VCC = VCC max, VIN =
47、 VCC max or VSS 1, 2, 3 All -10 +10 A Output leakage current ILO VCC = VCC max, VOUT = VCC max or VSS 1, 2, 3 All -10 +10 A VCC standby current (TTL) ICCS1 VCC = VCC max, CE = VIH 1, 2, 3 All 3.0 mA VCC standby current (CMOS) ICCS2 VCC = VCC max, CE = VCC 0.2 V 1, 2, 3 All 300 A VCC active read curr
48、ent ICC VCC = VCC max, CE = VIL IOUT = 0 mA, f = 5.0 V MHz, OE = VIH 1, 2, 3 All 50 mA Low level input voltage VIL 1, 2, 3 All -0.5 2/ 0.8 V High level input voltage (TTL) VIH1 1, 2, 3 All 2.0 VCC +0.5 2/ V High level input voltage (CMOS) VIH2 1, 2, 3 All VCC 0.3 VCC +0.5 2/ V Low level output volta
49、ge VOL IOL = 2.1 mA, VCC = VCC min 1, 2, 3 All 0.45 V High level output voltage (TTL) VOH1 IOH = -400 A, VCC = VCC min 1, 2, 3 All 2.4 V High level output voltage (CMOS) VOH2 IOH = -100 A, VCC = VCC min 1, 2, 3 All VCC 0.4 2/ V A9 auto select voltage VID A9 = VID 1, 2, 3 All 11.5 13.0 V A9 auto select current IID A9
