DLA SMD-5962-92252 REV E-2011 MICROCIRCUIT MEMORY DIGITAL CMOS 5000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

上传人:赵齐羽 文档编号:700219 上传时间:2019-01-01 格式:PDF 页数:36 大小:338.79KB
下载 相关 举报
DLA SMD-5962-92252 REV E-2011 MICROCIRCUIT MEMORY DIGITAL CMOS 5000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf_第1页
第1页 / 共36页
DLA SMD-5962-92252 REV E-2011 MICROCIRCUIT MEMORY DIGITAL CMOS 5000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf_第2页
第2页 / 共36页
DLA SMD-5962-92252 REV E-2011 MICROCIRCUIT MEMORY DIGITAL CMOS 5000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf_第3页
第3页 / 共36页
DLA SMD-5962-92252 REV E-2011 MICROCIRCUIT MEMORY DIGITAL CMOS 5000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf_第4页
第4页 / 共36页
DLA SMD-5962-92252 REV E-2011 MICROCIRCUIT MEMORY DIGITAL CMOS 5000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf_第5页
第5页 / 共36页
点击查看更多>>
资源描述

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added changes in accordance with NOR 5962-R154-95. 95-06-16 M. A. Frye B Added device type 03. Editorial changes throughout. 95-12-05 M. A. Frye C Changes in accordance with NOR 5962-R006-97. 96-10-04 Ray Monnin D Update drawing to current requir

2、ements. Editorial changes throughout. - gap 02-03-13 Ray Monnin E Updated boilerplate for 5 year review. - lhl 11-05-16 Charles F. Saffle REV E SHET 35 REV E E E E E E E E E E E E E E E E E E E E SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV E E E E E E E E E E E E

3、 E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RAJESH PITHADIA DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY KENNETH RICE THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY MICHAEL FRYE MICROC

4、IRCUIT, MEMORY, DIGITAL, CMOS 5000 GATE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-10-22 AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-92252 SHEET 1 OF 35 DSCC FORM 2233 APR 97 5962-E328-11 Provided by IHSNot for ResaleNo r

5、eproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92252 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of

6、high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 P

7、IN. The PIN is as shown in the following example: 5962 - 92252 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V

8、 RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2

9、.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 4005-10 5000 gate programmable array 10 ns 02 4005-6 5000 gate programmable array 6 ns 03 4005-5 5000 gate programmable array 5 ns 1.2.3 Device class designator.

10、 The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix

11、 A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA8-156 156 1/ Pin grid array package Y See figure 1 164 Quad flat package Z See f

12、igure 1 164 Quad flat package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ 156 = actual number of pins used, not maximum listed in MIL-STD-1835 Provided by IHSNot for ResaleNo reproduction or netw

13、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92252 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage range to ground potential (VCC) . -0.5 V dc to +7.0 V dc DC inp

14、ut voltage range -0.5 V dc to VCC+0.5 V dc Voltage applied to three-state output(VTS) . -0.5 V dc to VCC+0.5 V dc Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Case outline X See MIL-STD-1835 Case outlines Y and Z . 20C/W 3/ Junction temperature (TJ) . +15

15、0C 4/ Storage temperature range -65C to +150C 1.4 Recommended operating conditions. 5/ Case operating temperature Range (TC) -55C to +125C Supply voltage relative to ground (VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) 0 V dc 2. APPLICABLE DOCUMENTS 2.1 Government specification,

16、standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - I

17、ntegrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings.

18、 MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 2/ Stresses above the absolute maximum rating may c

19、ause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ When a thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated herein. 4/ Maximum junction temperature shall not be ex

20、ceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 5/ All voltage values in this drawing are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUI

21、T DRAWING SIZE A 5962-92252 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents

22、 cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S Arlington, V

23、A 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. R

24、EQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or

25、 function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions sha

26、ll be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specifi

27、ed on figure 2. 3.2.3 Logic block diagram. The logic block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits ar

28、e as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be ma

29、rked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option

30、, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be

31、a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to suppl

32、y to the requirements of this drawing (see 6.7.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.7.2 herein). The certificate of compliance submitted to DLA Land and Maritime-V

33、A prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conforma

34、nce. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to

35、DLA Land and Maritime -VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962

36、-92252 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers faci

37、lity and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendi

38、x A). 3.11 Operational notes. Additional information shall be provided by the device manufacturer (see 6.6 herein). 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manuf

39、acturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening s

40、hall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspe

41、ction. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (pre-burn-in) electrical parameters through interim (post-burn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. b. For device class M, the test circuit shall

42、 be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. For device class M, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the inten

43、t specified in method 1015. (1) Static burn-in for device classes M, Q, and V (method 1015 of MIL-STD-883, test condition A). (a) All inputs shall be connected to GND. Outputs may be open or connected to 5.0 V + 0.5 - 0.0 V minimum. Resistors R1 are optional on both inputs and outputs, and required

44、on outputs connected to VCC+ 0.5 - 0.0 V. R1 = 220 to 47 k. For static II burn-in, reverse all input connections (i.e., VSSto VCC). (b) VCC= 5.0 V + 0.5 V - 0.0 V minimum. (2) TA= +125C, minimum. c. Interim and final electrical test parameters shall be as specified in table IIA herein. 4.2.2 Additio

45、nal criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level

46、control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the

47、 intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspe

48、ction for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92252 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E

展开阅读全文
相关资源
猜你喜欢
相关搜索

当前位置:首页 > 标准规范 > 国际标准 > 其他

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1