1、-1- JEDEC PUBLICATION Understanding Electrical Overstress - EOS JEP174 SEPTEMBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed
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9、240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 174 -i- UNDERSTANDING ELECTRICAL OVERSTRESS - EOS Contents Introduction . iii I.1 Purpose iii I.2 Traditional Perceptions of EOS . iv I.3 Industry Council Worldwide Sur
10、vey . iv I.4 New Definition of EOS Incorporating AMR and EIPD . v I.5 EOS Root Causes . vii I.6 EOS Root Cause Diagnostics viii I.7 EOS Case Studies and IC Designs ix I.8 EOS Mitigation and Communication . x I.9 Summary x I.10 Outlook. x 1 Scope 1 2 References . 1 3 Terms and Definitions 7 4 History
11、 of EOS . 9 4.1 Outline of History of Relevant Professional Societies . 11 4.2 EOS A Brief History . 11 4.3 Transition to Present 14 5 EOS Damage in the Factory and Field . 15 5.1 Motivation for Field Returns Analysis of Failures Exhibiting EOS Damage 15 5.2 Transients . 16 5.3 EOS Survey for Gather
12、ing Data on EOS Damage . 17 5.4 Impact of EOS Damage . 32 5.5 Failure Reports of Products Exhibiting EOS Damage . 33 6 The Definition of EOS Finding Common Understanding 34 6.1 Existing Documentation Practices of AMR Values . 35 6.2 Unified Understanding of AMR and EOS 37 6.3 Additional Comments on
13、Usage of the Term “EOS” . 38 6.4 Conclusion . 38 7 EOS Root Causes 39 7.1 Root Cause Categories . 39 7.2 EOS Damage during Unpowered Handling . 40 7.3 EOS during Powered Handling 43 7.4 EOS Damage during AC Operation and Switching . 47 7.5 Analysis of Electrically Induced Physical Damage and Conclus
14、ions on EOS Events . 48 8 Case Studies on EOS 50 8.1 Case 1: Incorrect ESD Qualification Leading to EOS . 51 8.2 Case 2: EOS Due to Misapplication . 54 8.3 Case 3: EOS due to Hot Plugging 57 8.4 Case 4: EOS due to Intermittent Battery Ground Connection 61 8.5 Case 5: EOS due to Ground Offset 63 8.6
15、Case 6: EOS Case Study “Automotive Knock Sensor“ 65 8.7 Case 7: EMI Transient Surge 70 8.8 Case 8: EMI Board Design 73 8.9 Case 9: Supply Capacitor Switching 76 8.10 Case 10: CBE in DSP IC 78 8.11 Case 11: Reliability Testing . 83 8.12 Lessons Learned . 88 8.13 Conclusions 88 JEDEC Publication No. 1
16、74 -ii- 9 EOS Analysis and Diagnosis - “Techniques and Methods for Dealing with Electrically Induced Physical Damage” 89 9.1 Optimal Customer and Supplier Failure Symptom Information Exchange and Device Handling . 89 9.2 EOS FA Challenges . 90 9.3 High Level Preparation Guidelines for Diagnosing the
17、 Cause of EOS 92 9.4 Failure Analysis Techniques and Procedures . 92 9.5 Analysis of Damage Mechanisms for EOS 102 9.6 Overstress Power vs. Time . 107 9.7 Final Diagnosis of the Cause and Conclusion 108 10 Minimization and Mitigation of EOS . 112 10.1 Lessons Learned to Minimize EOS Damage 112 10.2
18、Automotive Studies 117 10.3 Integrated Circuit Trends and EOS Effects 122 10.4 Communication with Customers 134 10.5 Recommendations for EOS Minimization and Mitigation . 136 10.6 Conclusions 137 11 Summary and Conclusions 138 Annex A: EOS Survey Form . 140 Annex B: The Dwyer Curve and EOS Damage at
19、 a Temperature Threshold 146 B.0 Background and 1-Dimensional Heat Flow . 146 B.1 Heat Flow as an RC Transmission Line . 147 B.2 Thermal Impedance and the Jacobi Theta4 Function . 148 B.3 The Analytic Dwyer Curve Approximation . 150 B.4 Utility of the Dwyer Curve and Thermal Impedance Approximations
20、 155 Annex C: Frequently Asked Questions . 156 JEDEC Publication No. 174 -iii- Foreword Damage signatures from Electrical Overstress (EOS) are the leading reported cause of returns in integrated circuits and systems that have failed during operation. Solutions to this problem are hindered by a preva
21、iling misconception in the electronics industry that insufficient robustness to electrostatic discharge (ESD) is a primary cause of EOS. This document, White Paper 4, (WP) has been carefully compiled by the Industry Council on ESD Target Levels to foster a unified global understanding of what consti
22、tutes EOS and how EOS damage signatures can result from a wide variety of root causes. The paper begins by outlining a brief history of EOS. It then presents the results of an industry-wide EOS survey. This survey gathered information on the types of EOS problems experienced by over 80 different com
23、panies, the relative importance of EOS to their overall business, and the methods assigned by these companies to address EOS issues. The survey provides a combined picture from which a more comprehensive definition of EOS can be made. The numerous categories and sub-categories of EOS root causes are
24、 explored in an attempt to understand how to create better specifications which will reduce their occurrence. In addition to the survey results, this paper studies many field returns with EOS damage signatures to establish the underlying root causes of damage and offers the respective identified sol
25、utions. The survey and the case studies both show that successful failure analysis (FA) depends on careful communication between customer and supplier from the time a failure occurs until its cause has been discovered. Detailed investigation into manufacturing and handling processes is often necessa
26、ry to accurately identify the root cause. This paper outlines a basic summery of the typical process flow for component electrical failure analysis. The key point is that EOS issues can be mitigated when the proper understanding of IC design, factory and field environments, and system implementation
27、 is combined with effective communication across all these areas. Introduction In this introduction the Industry Council will address the most important electrical overstress (EOS) issues and conclusions of White Paper 4. Further details can be found in the various clauses of the document. I.1 Purpo
28、se This purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper
29、is to clarify what EOS really is and how it can be mitigated once it is properly comprehended. It is very clear that EOS is predominantly a matter of what customers do with devices, and in which applications the semiconductor specifications are exceeded causing destruction of the device. This white
30、paper will describe those phenomena and explain the most important facts so that the involved partners in the industry have the opportunity to understand and recognize helpful steps for analysis and avoidance of EOS events. JEDEC Publication No. 174 -iv- I.1 Introduction (contd) EOS is defined in te
31、rms of its impact inside applications. We focus on exceedance of specifications but not on how an exact specification was originally created. We focus instead on when and how the specifications are exceeded to cause EOS damage. It is intended that this document be disseminated throughout the semicon
32、ductor industry for the benefit of those persons whose positions are concerned with the real nature of EOS. It is intended to serve as a foundational reference document for existing and future technologies. I.2 Traditional Perceptions of EOS Through the years, a high incidence of failures exhibiting
33、 EOS damage has been reported in most market segments of electronics and related industries, such as the automotive industry. This damage has often been mislabeled as “EOS Failure”, implying that these malfunctions are solely a result of a phenomenon or stress called EOS. Understanding EOS as a “str
34、ess” has led many customers to incorrectly assume a device experiencing EOS is “weak”. This misperception has led to requests to “improve” a device in regards to EOS. Another incorrect assumption has been that EOS can be avoided by making devices more ESD robust to both the human body model (HBM) an
35、d the charged device model (CDM). This misconception has been addressed in JEDEC publications JEP155 1, and JEP157 2 where it is convincingly shown that the incidence of EOS is independent of the level of HBM and CDM robustness. I.3 Industry Council Worldwide Survey In preparation for this white pap
36、er, the Industry Council conducted a worldwide survey of the electronics industry concerning EOS. Results confirmed the long held view that EOS is consistently one of the “high bars” on product failure Pareto charts. Looking at the EOS survey, respondents reported greater than 20% of total failures
37、being EOS-related or 30% of total electrical failures being EOS-related, making EOS the largest bar on the Pareto chart of that responders known causes of returns. One glaring revelation was the critical need for a better industry-wide understanding of EOS to address its issues. Looking at the EOS s
38、urvey further, misapplication (powered handling) stands out as the highest cause of EOS damage, with over 40% of respondents indicating EOS damage which occurred in the field as the most common location. Damage signatures associated with EOS often can involve package and silicon damage and are more
39、extensive in a product than failure signatures resulting from events in the measurable ESD regimes. The main findings of the EOS Survey were: 1) Powered Handling: This stands out as the most widely reported root cause, involving a significant (over 20%) percentage of reported returns exhibiting EOS
40、damage. Powered handling can include overvoltage, improper insertion, power supply sequencing, and incorrect biasing during use. 2) Absolute Maximum Rating (AMR): A number of returns exhibiting EOS damage were attributed to applied voltages exceeding the specified AMR voltage, indicating that incomp
41、lete or unclear maximum ratings may be an issue and that AMR characterization and improved AMR information on the datasheets is important to minimize the risk of EOS. 3) ESD Related: System level events, discharges from charged devices, and ESD controls in manufacturing which are not compliant with
42、handling ESDS devices are additional root causes for EOS damage. Charged board events (CBE) and cable discharge events (CDE) also contribute. 4) Miscellaneous Causes: There were other miscellaneous causes reported that ranged from weak printed circuit board (PCB) designs to mishandling. JEDEC Public
43、ation No. 174 -v- I.4 New Definition of EOS Incorporating AMR and EIPD It became clear to the Council during analysis of the survey, as well as gathering data on customersupplier experiences with resolving EOS-related returns that a new way of visualizing the relationship of AMR to EOS is sorely nee
44、ded in the industry. The Council proposes that the relationship between EOS and AMR may be illustrated in the manner indicated in Figure 1. Definition of AMR and its relationship to device stress, reliability impact and long and short term damage potential allows semiconductor manufacturers to clear
45、ly provide the maximum voltage / current / power limits. This enables system manufacturers to incorporate devices into their systems safely and ensure an operational environment that does not exceed those maximum limits. This is based on the following EOS definition: An electrical device suffers an
46、electrical overstress event when a maximum limit for either the voltage across, the current through, or power dissipated in the device is exceeded and causes immediate damage or malfunction, or latent damage resulting in an unpredictable reduction of its lifetime. Critical to this definition is a cl
47、ear understanding of what is meant by maximum limit. Clause 6 further expands this definition by providing a practical interpretation of EOS in terms of AMR. Insight into the electrical aspects of AMR can be gained by examining the voltage ranges illustrated in Figure 1. Figure 1 A graphical depicti
48、on of how Absolute Maximum Ratings should be interpreted. (The yellow line is the number of components suffering immediate, catastrophic EOS damage.) First, there is the safe operating area, a region of robust operation (region A). This is the region in which the manufacturer designed the device to
49、operate. This is followed by a region in which operating restrictions exist (region B). In region B, the device is not guaranteed to function as specified, however the device is not expected to be physically damaged. Operating the device in region B for extended periods of time may also result in reliability issues. The upper limit of region B is the AMR. At and beyond the AMR the user should expect problems. Beyond the AMR are two regions of electrical overstress with either latent (region C) or immediate (region D) damage as a result of exceeding AMR. Note that the transit
