1、_SAE Technical Standards Board Rules provide that: “This report is published by SAE to advance the state of technical and engineering sciences. The use of this report is entirely voluntary, and its applicability and suitability for any particular use, including any patent infringement arising theref
2、rom, is the sole responsibility of the user.”SAE reviews each technical report at least every five years at which time it may be revised, reaffirmed, stabilized, or cancelled. SAE invites your written comments and suggestions.Copyright 2015 SAE InternationalAll rights reserved. No part of this publi
3、cation may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of SAE.TO PLACE A DOCUMENT ORDER: Tel: 877-606-7323 (inside USA and Canada)Tel: +1 724-776-4970 (out
4、side USA)Fax: 724-776-0790Email: CustomerServicesae.orgSAE WEB ADDRESS: http:/www.sae.orgSAE values your input. To provide feedbackon this Technical Report, please visithttp:/www.sae.org/technical/standards/ARP6338AEROSPACERECOMMENDED PRACTICEARP6338Issued 2015-12Process for Assessment and Mitigatio
5、n of Early Wearout of Life-limited MicrocircuitsRATIONALEAs microcircuit technology progresses, the risk of early wearout increases for aerospace users. The aerospace industry needs to have a standardized approach to analysis and testing for wearout, to ensure reliability of future products, without
6、 introducing competitive disadvantages to those who address the issue effectively.FOREWORDThis document describes processes to assess and mitigate the effects of early wearout in life-limited microcircuits (LLM) used in aerospace, defense, and high-performance (ADHP) applications. As microcircuit te
7、chnology progresses to smaller and smaller feature sizes, early wearout in ADHP applications becomes an issue for ADHP design, part selection, and reliability assessment. Wearout failures are defined in this document as intrinsic failures resulting from material degradation in the active regions,die
8、lectrics, and conductors of silicon devices. Typically, such failures occur according to non-random, or non-constant, failure rate distributions, and are thus expressed in terms of “time-to-failure,” or “failure fraction.” Early wearout occurs when the microcircuit lifetime is shorter than the time
9、it is required to operate in the ADHP equipment.This document does not address package failures. Neither does it address extrinsic random failures that occur according to constant or decreasing failure rate distributions, which are usually expressed in terms of “mean time between failures.” This doc
10、ument considers the following failure mechanisms: electromigration (EM), time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), and bias temperature instability (BTI)1. Depending on the device design, materials, and fabrication technology, one of these mechanisms is likely to domin
11、ate in any given ADHP application.Most of the microcircuits used in ADHP applications today are commercial-off-the-shelf (COTS) components targeted for markets other than ADHP; and the required lifetimes in the target markets typically are significantly shorter than those of ADHP applications. COTS
12、component manufacturers evaluate their components expected lifetimes in the target applications, but provide little or no information for ADHP applications. Thus it is the responsibility of the ADHP user to conduct the appropriate analyses and, where necessary, provide mitigations for shorter-than-r
13、equired lifetimes.1Other life-limiting failure mechanisms also may occur in any given ADHP application, and their effects should be considered where appropriate.SAE INTERNATIONAL ARP6338 Page 2 of 141. SCOPEThis document is intended for use by designers, reliability engineers, and others associated
14、with the design, production, and support of electronic sub-assemblies, assemblies, and equipment used in ADHP applications to conduct lifetime assessments of microcircuits with the potential for early wearout; and to implement mitigations when required; and by the users of the ADHP equipment to asse
15、ss those designs and mitigations.This document focuses on the LLM wearout assessment process. It acknowledges that the ADHP system design process also includes related risk mitigation and management; however, this document includes only high-level reference and discussion of those topics, in order t
16、o show their relationship to the LLM assessment process.2. REFERENCES1. Failure Mechanisms and Models for Semiconductor Devices, JEP122, JEDEC.2. Early Life Failure Rate Calculation Procedure for Electronic Components, JESD74, JEDEC.3. Physics of Failure Reliability Predictions, ANSI/VITA 51.2-2011,
17、 VITA.4. Customer Notification of Product/Process Changes by Solid-State Suppliers, JESD46, JEDEC.5. Information Requirements for the Qualification of Silicon Devices, JESD69, JEDEC.6. Method for Developing Acceleration Models for Electronic Component Failure Mechanisms, JESD91, JEDEC.7. Solid-State
18、 Reliability Assessment and Qualification Methodologies, JEP143, JEDEC.3. LIFE-LIMITED MICROCIRCUIT IDENTIFICATION, ASSESSMENT, AND MITIGATION PROCESSThis clause describes the process for lifetime assessment of microcircuits. It also includes brief descriptions of risk analysis and mitigation method
19、s for early wearout. The process is illustrated by the flow diagram in Appendix A2.3.1 Application RequirementsIdentify and document the required environmental and operating conditions that have the potential to impact the lifetime of microcircuits. Examples are: ambient temperature, junction temper
20、ature, operating voltage, duty cycle, etc.3.2 IdentificationIdentify all potential LLM in the sub-assembly, assembly, and equipment that are subject to early wearout in the ADHP application due to the combined effects of the following failure mechanisms: Electromigration (EM), Time-dependent Dielect
21、ric Breakdown (TDDB), Hot Carrier Injection (HCI), and Bias Temperature Instability (BTI).(Include all microcircuits on the parts list of the ADHP equipment for which the component lifetime in the application cannot be assured by the component data sheet or other device manufacturer information. Typ
22、ically, the list includes, as a minimum, COTS microcircuits with feature sizes less than 50 nanometers (nm).(Appendix B illustrates a format that can be used to list the identified microcircuits, and describe their application requirements.)2The processes described in this clause are intended for us
23、e at the microcircuit level; however, they are equally applicable to key performance functional groups (KPFG) within microcircuits. If sufficient knowledge exists, the user is encouraged to perform the assessment(s) at the KPFG level.SAE INTERNATIONAL ARP6338 Page 3 of 143.3 Application-specific Ass
24、essment by the LLM ManufacturerThe most credible assessment, and the one most preferred3, is an estimate of the expected lifetime of the LLM in the ADHP application, provided by the manufacturer of LLM, based on the manufacturers test data, acceleration models, design information, materials, and pro
25、duction technology for the specific microcircuit or microcircuit family, and also on the use conditions of the application.3.4 Application-specific Assessment by the LLM User with Applicable In-service DataIn cases where the LLM user has in-service data from similar LLM in similar applications, the
26、assessment includes a comparison of the in-service data with the proposed use, with modifications made to account for differences, within limits described in detail by the LLM user.3.5 Analysis by the LLM UserThe analysis process includes two major elements: (1) relevant test data, as described in o
27、rder of preference in 3.5.1.1, 3.5.1.2, and 3.5.1.3; and (2) credible acceleration models, as described in order of preference in 3.5.2.1, 3.5.2.2, and 3.5.5.3.(Appendix C contains guidance regarding the use of data and acceleration models from various sources.)3.5.1 Test DataThe three major categor
28、ies of relevant data are listed below, in order of preference.3.5.1.1 LLM Manufacturer DataExamples are:x Data from accelerated stress tests, e.g., HTOL designed and conducted by the LLM manufacturer;x Data from tests conducted on primitive structures during development by the LLM manufacturer; andx
29、 Data obtained by the LLM manufacturer regarding performance of their products in service.Relevant data could be from tests conducted on the specific microcircuit, or microcircuits with similar technology, size, etc.; or from data conducted on primitive test structures representing the structures of
30、 the specific microcircuit.Relevant data could be a subset of qualification tests or periodic product or process monitoring.3.5.1.2 LLM User DataCredible data from tests designed and conducted by the LLM user are based on a physics-of-failure (PoF) based understanding of the susceptibility of the de
31、vice to the four major failure mechanisms. Typically, such tests are similar to those defined and conducted by the LLM manufacturer.3Although this is typically the case, it is not always so. For example, there may be in-service data available for the specific microcircuit in nearly-identical operati
32、ng environments that are more credible than estimates from the microcircuit manufacturer. SAE INTERNATIONAL ARP6338 Page 4 of 143.5.1.3 Generic DataGeneric data are obtained from tests of the specific microcircuit, performed by a party other than the LLM manufacturer or user. Examples include:x Test
33、 data from the LLM manufacturer or the user on a device that is substantially similar to the device used in the ADHP application;x Test data reported in the literature, for the LLM used in the ADHP application, or one substantially similar to it;x In-service failure or reliability data from the LLM
34、used in the application, or one substantially similar to it;x Other data that can be demonstrated as relevant.3.5.2 Acceleration ModelsAcceleration models are used to translate test data to estimates of the expected lifetime of a given microcircuit, with respect to each of the four major life-limiti
35、ng failure mechanisms: Electromigration (EM), Time-dependent Dielectric Breakdown (TDDB), Hot Carrier Injection (HCI), and Bias Temperature Instability (BTI). Examples of acceleration models are shown in Appendix C. Further examples and explanations of acceleration models may be found in References
36、1, 2, and 3. Reference 4 describes the models in Appendix C in more detail.Acceptable acceleration models include terms to describe the stresses on the LLM, including:x Operating stresses such as voltage, current, electrical field strength, frequency, etc.x Environmental stresses such as temperature
37、, temperature variations, etc.Acceptable acceleration models are at least as rigorous as those shown in Appendix D.The three major categories of acceleration models are listed below, in order of preference.3.5.2.1 LLM Manufacturer ModelsMost microcircuit manufacturers develop their own models during
38、 the product development process. Although there is a high degree of similarity among manufacturers and product types, the models may vary due to design processes, materials, and production processes. Microcircuit manufacturers models are preferred over other models; however, most of those models ar
39、e proprietary to the manufacturer.3.5.2.2 LLM User ModelsSome ADHP users of microcircuits have sufficient test, analysis, and design capability to develop their own versions of acceleration models for specific LLM in specific applications. These models are acceptable, provided that they can be shown
40、 to be equivalent or better than those shown in Appendix D.3.5.2.3 Generic ModelsIn the absence of models developed by the LLM manufacturer or user, credible generic acceleration models may be obtained from published literature. These models also are acceptable, provided that they can be shown to be
41、 equivalent or better than those shown in Appendix D.SAE INTERNATIONAL ARP6338 Page 5 of 143.6 Alternative MethodsAlternative assessment methods are acceptable when they can be shown to be superior to the process described above, or acceptable in the application. Such methods are agreed upon by the
42、LLM user, i.e., ADHP equipment manufacturer, and the ADHP equipment customer.Appendix F contains descriptions of some software tools that are commonly used for this purpose. (This is not an endorsement by this document or SAE of any of the tools listed in Appendix F.)3.7 Mitigation Methods and Risk
43、AnalysisFor each microcircuit whose assessed wearout lifetime, with respect to the failure mechanisms listed in 3.2, is less than that required by the equipment, define and implement measures to increase the lifetime, or otherwise mitigate the effects of early wearout. Example mitigation measures ar
44、e discussed in Appendix E.For all LLM, including both those for which mitigation methods have been used, and those without mitigation methods, define the risks that still exist. Risks include (a) the probability that a negative event will occur, and (b) the cost of occurrence of the negative event.
45、Risk analysis could include Failure Modes, Effects, and Criticality Analysis (FMECA), Fault Tree Analysis, or other formal methods. Risk analysis also could include less formal methods; and in all cases, quantifying the risk is highly desirable. The goal of risk analysis is to provide sufficient inf
46、ormation for the ADHP manufacturer and the customer to determine what is acceptable with regard to the LLM usage.4. REPORTFor each microcircuit, prepare a report containing the following information:x Microcircuit description;x Required wearout lifetime;x Assessed lifetime (expected wearout mechanis
47、m(s), expected lifetime, etc.);x Mitigation methods (if required); andx Other relevant information.The format of Appendix G is recommended.5. TERMS, DEFINITIONS, ABBREVIATIONS, AND ACRONYMSADHP - Aerospace, Defense, and High Performance; used to define a class of electronic equipment characterized b
48、y long service lifetime, rugged operating conditions, and high consequences of failure.BIAS TEMPERATURE INSTABILITY (BTI) - A semiconductor device failure mechanism in which interface traps and electrical charges are generated in CMOS devices. Negative bias temperature instability (NBTI) is generate
49、d under negative gate bias, and positive bias temperature instability is generated in positive gate bias.CMOS - Complementary metal oxide semiconductorCOTS - Commercial-off-the-shelfEARLY WEAROUT - Wearout of a semiconductor device prior to the time it is required to operate in the application.ELECTROMIGRATION (EM) - Transport of material caused by the gradual movement of the ions in a conductor due to the momen
