1、Developed byINCITS TR-33-2003INCITS Technical Reportfor Information Technology Fibre Channel Signal Modeling (FCSM)Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-INCITS TR-33-20
2、03INCITS Technical ReportInformation Technology Fibre Channel Signal Modeling (FCSM)SecretariatInformation Technology Industry CouncilABSTRACTThis technical report is intended to establish a common methodology so that signals in FC systems may bemodeled and simulated accurately and consistently. It
3、establishes the requirements for the exchange ofperformance information between components suppliers and system simulators. It defines the acceptablemethods for extracting the electrical and performance attributes of the constituent parts of the FC copperand optical interface. It establishes a commo
4、n methodology for simulating the FC physical environment. Itis intended to be used in conjunction with the requirements within the following documents: FC PhysicalInterface (FC-PI; T11/1235-D), FC Physical Interface-2 (FC-PI-2; T11/1506-D), and FC 10 Gigabit (10GFC;T11/1413-D).Copyright American Nat
5、ional Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Published byAmerican National Standards Institute25 West 43rd Street, New York, New York 10036Copyright 2003 by Information Technology Industry Council
6、(ITI)All rights reserved.No part of this publication may be reproduced in anyform, in an electronic retrieval system or otherwise, without prior written permission of the publisher.Printed in the United States of AmericaINCITS Technical Report Series This Technical Report is one in a series produced
7、 by the International Committeefor Information Technology Standards (INCITS). The secretariat for INCITS is heldby the Information Technology Industry Council (ITI), 1250 Eye Street, NW, Suite200, Washington, DC 2005.As a by-product of the standards development process and the resources ofknowledge
8、devoted to it, INCITS from time to time produces Technical Reports.Such Technical Reports are not standards, nor are they intended to be used assuch.INCITS Technical Reports are produced in some cases to disseminate thetechnical and logical concepts reflected in standards already published or underd
9、evelopment. In other cases, they derive from studies in areas where it is foundpremature to develop a standard due to a still changing technology, orinappropriate to develop a rigorous standard due to the existence of a number ofviable options, the choice of which depends on the users particular req
10、uirements.These Technical Reports, thus, provide guidelines, the use of which can result ingreater consistency and coherence of information processing systems.When the draft Technical Report is completed, the Technical Committee approvalprocess is the same as for a draft standard. Processing by INCI
11、TS is also similarto that for a draft standard.Patent StatementCAUTION: The developers of this Technical Report have requested that holdersof patents that may be required for the implementation of the standard, disclosesuch patents to the publisher. However, neither the developers nor the publisherh
12、ave undertaken a patent search in order to identify which, if any, patents mayapply to this Technical Report. As of the date of publication of this Technical Report and following calls for theidentification of patents that may be required for the implementation of theTechnical Report, no such claims
13、 have been made. No further patent search isconducted by the developer or the publisher in respect to any Technical Report itprocesses. No representation is made or implied that licenses are not required toavoid infringement in the use of this Technical Report.Copyright American National Standards I
14、nstitute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Table of Contents1 Scope .12 References .22.1 General .22.2 Approved references .22.3 References under development 22.4 Informative references 32.4.1 Electrical 32.4.2 O
15、ptical .32.5 Resources bibliography .33 Definitions, acronyms, symbols, abbreviations, keywords, and conventions .53.1 Definitions .53.2 Symbols, abbreviations, and acronyms 143.2.1 Symbols 143.2.2 Acronyms and other abbreviations 163.3 Keywords 173.4 Conventions 174 General .194.1 Overview .194.2 S
16、ignal path architectures for modeling 194.2.1 Transmitter-receiver connection 194.2.2 Copper transmitter-receiver connection 194.2.3 Optical transmitter-receiver connection .204.3 Relationship between FCSM and bit errors 214.4 FCSM and scaling .214.5 Range of validity of models and simulations .224.
17、6 Signal modeling purposes .224.6.1 Overview .224.6.2 Physical components and signals .234.6.2.1 Relationship between physical and modeling terminology 234.6.2.2 Elemental components 234.6.2.3 Composite components .244.6.2.4 Systems .244.6.2.5 Signals and measurement points 254.6.2.6 Modeling run le
18、ngth dependent transmitter signals .274.6.2.7 Interactions between signals on different signal lines 284.6.3 Data patterns .284.6.4 Viewpoints .284.7 Application to measurement 304.8 Relationship between elemental component models, composite component models, model-ele-ments, and simulation 314.9 Sp
19、ecification of the simulation and the simulation environment 334.10 Specification of signals at interoperability points .334.11 Transmitter signals, interconnect, and receivers that contain compensation properties (equaliza-tion) 334.11.1 Compensation .334.11.2 Transmitter compensation .344.11.3 Int
20、erconnect compensation .354.11.4 Receiver compensation .354.12 Approaches to creating component models 364.12.1 Create the model from samples of physical components .36Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking p
21、ermitted without license from IHS-,-,-Table of Contents4.12.1.1 Behavioral extraction from a linear component .364.12.1.2 Fitted circuit parameters 364.12.1.3 SPICE device model 364.12.2 Creating the model from design information .364.13 Practical considerations for creating models .374.14 Relations
22、hip between constituents of the modeling environment .384.15 Relationship between signal specifications in standards and modeling 394.16 Accuracy and model validation considerations .394.17 Component model validation/correlation methods 404.17.1 Overview .404.17.2 Range of validity 404.17.3 Method 1
23、 (simultaneous creation and validation) 414.17.4 Method 2 (validation of extracted parameters for elemental components) .414.18 Signal timing reference in simulations .414.19 Tools .424.19.1 Overview .424.19.2 Simulation tools .424.19.3 Parameter extraction tools 434.19.4 Model creation tools 435 Mo
24、del-element descriptions 445.1 Overview .445.2 Circuit description 445.3 Behavioral description - linear parameters 445.4 Behavioral description - RLGC matrix (Maxwell matrix) 465.4.1 Overview .465.4.2 RLGC matrices for general construction .465.4.3 An 11 conductor example .475.5 Behavioral descript
25、ion - mathematical function .535.6 Behavioral description - IBIS .536 Transportable models .556.1 General requirements .556.1.1 Overview .556.1.2 Documentation 556.1.3 Model Name 556.1.4 Model class .566.1.5 Model boundary 566.1.6 Model limitations and dependencies .566.1.7 Model creation methodolog
26、y .566.1.7.1 Overview 566.1.7.2 Model creation stimuli 566.1.7.3 Amplitude and timing .566.1.7.4 Frequency range .566.1.7.5 Rise time 566.1.8 Model validation 566.1.8.1 Overview 566.1.8.2 Accuracy requirements 576.1.8.3 Model validation stimuli 576.1.8.4 Amplitude and timing .576.1.8.5 Frequency ran
27、ge .576.1.8.6 Rise time 576.2 Component models examples .57Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Table of Contents6.2.1 Overview .576.2.2 Copper cable assembly - compos
28、ite component 586.2.2.1 Overview 586.2.2.2 Cable assembly model boundary 586.2.2.3 Cable assembly model class .586.2.2.4 Relative position of all the elemental components .586.2.2.5 Specification of each elemental component model .586.2.2.5.1 Mated connector pair 586.2.2.5.1.1 Elemental component mo
29、del boundary 586.2.2.5.1.2 Model-elements in the elemental component .586.2.2.5.1.2.1 Model element types 586.2.2.5.1.2.2 Model-element creation methodology 586.2.2.5.1.2.3 Model-element detailed description .586.2.2.5.2 Transition region .596.2.2.5.2.1 Elemental component model boundary 596.2.2.5.2
30、.2 Model-elements in the elemental component .596.2.2.5.2.2.1 Model element types 596.2.2.5.2.2.2 Model-element creation methodology 596.2.2.5.2.2.3 Model-element detailed description .596.2.2.5.3 Bulk cable .596.2.2.5.3.1 Elemental component model boundary 596.2.2.5.3.2 Model-elements in the elemen
31、tal component .596.2.2.5.3.2.1 Model element types 596.2.2.5.3.2.2 Model-element creation methodology 596.2.2.5.3.2.3 Model-element detailed description .596.2.2.5.4 Composite component model validation methodology .596.2.3 Host bus adapter board - composite model 606.2.3.1 Overview 606.2.3.2 Host b
32、us adapter model boundary .606.2.3.3 Host bus adapter model class .606.2.3.4 Relative position of all the elemental components .606.2.3.5 Specification of each elemental component model .606.2.3.5.1 Electrical transceiver 606.2.3.5.1.1 Elemental component model boundary - electrical transceiver 606.
33、2.3.5.1.2 Model-elements in the elemental component - electrical transceiver .606.2.3.5.1.2.1 Model element types 606.2.3.5.1.2.2 Model-element creation methodology - electrical transceiver 606.2.3.5.1.2.3 Model-element detailed description - electrical transceiver .606.2.3.5.2 PCB 606.2.3.5.2.1 Rel
34、ative position of model-elements in elemental component - PCB .606.2.3.5.2.2 Chip pad / connector pad 616.2.3.5.2.2.1 Model element boundary - chip pad / connector pad .616.2.3.5.2.2.2 Model-element class - chip pad / connector pad .616.2.3.5.2.2.3 Model-element creation methodology - chip pad / con
35、nector pad .616.2.3.5.2.2.4 Model-element detailed description - chip pad / connector pad 616.2.3.5.2.3 PCB trace 616.2.3.5.2.3.1 Model element boundary - PCB trace 616.2.3.5.2.3.2 Model-element class - PCB trace 616.2.3.5.2.3.3 Model-element creation methodology - PCB trace 616.2.3.5.2.3.4 Model-el
36、ement detailed description - PCB trace .616.2.3.5.2.4 Chip capacitor .616.2.3.5.2.4.1 Model element boundary -chip capacitor .616.2.3.5.2.4.2 Model-element class - chip capacitor 61Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or
37、 networking permitted without license from IHS-,-,-Table of Contents6.2.3.5.2.4.3 Model-element creation methodology - chip capacitor 616.2.3.5.2.4.4 Model-element detailed description - chip capacitor 61Annex A - Model database format 63A.1 Overview .63A.2 Database format 63Annex B - IBIS model cre
38、ation details 64B.1 Basic steps 64B.2 Pre-modeling activities 64B.2.1 Preliminary information required 64B.2.2 IBIS version .64B.2.3 Specific device .64B.2.4 Corner limits .65B.2.5 SSO effects 65B.2.6 Schematics 65B.2.7 Clamp diode and pullup references .65B.2.8 Packaging information .65B.2.9 Signal
39、 information 65B.2.10 Die capacitance .66B.2.11 Vinl and Vinh parameters 66B.2.12 Tco measurement conditions .66B.2.13 Buffer grouping 66B.3 Data extraction 66B.3.1 Switching and I/V information 66B.3.2 s2ibis extraction .66B.3.3 Direct simulation extraction 66B.3.3.1 Procedures for direct data extr
40、action 66B.3.3.2 Extracting I/V data 67B.3.3.3 Hi-Z buffers .67B.3.3.4 Output only buffer .68B.3.3.5 Open drain buffers 68B.3.3.6 Input buffers 68B.3.3.7 Sweep ranges .68B.3.3.8 Pullup and power clamp sweeps relative to Vdd 69B.3.3.9 Diode models 69B.3.3.10 Extracting the Ramp Rate or V/s Waveform D
41、ata 69B.3.3.11 Extracting Data for the Ramp Keyword 69B.3.3.12 Extracting Data for the Rising and Falling Waveform Keywords 70B.3.3.13 Minimum Time Step 71B.3.4 Direct measurement procedure .72B.4 Creating the IBIS file .72B.4.1 Overview 73B.4.2 Header Information 73B.4.3 Component and pin informati
42、on .74B.4.4 Model description .74B.4.4.1 Model keyword parameters 75B.4.4.2 Temperature Range and Voltage Range keywords 76B.4.4.3 I/V data section .76B.4.4.3.1 Pulldown keyword 77B.4.4.3.2 GND Clamp keyword .77B.4.4.3.3 Pullup keyword 77B.4.4.3.4 POWER Clamp keyword .78B.4.4.3.5 Clamp keyword extra
43、polation caveats .78B.4.5 Ramp keyword and waveform tables .78Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Table of ContentsB.4.6 IBIS file conformance .79B.5 IBIS model valid
44、ation 79B.6 IBIS model verification 80B.6.1 Overview 80B.6.2 Acceptance criteria 80Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Table of ContentsFigure 1 - Architecture for mo
45、deling a minimal copper transceiver path .19Figure 2 - Architecture for modeling an optical transmitter-receiver connection 20Figure 3 - Example of amplitude scaling 22Figure 4 - Tx interoperability points (examples) 26Figure 5 - Rx interoperability points (examples) 27Figure 6 - FCSM applicability
46、to a simple link 29Figure 7 - Modeling architecture for launching a specific signal at a connector 30Figure 8 - Measurement set up for evaluating transmitters 34Figure 9 - Measurement set up for evaluating receivers .35Figure 10 - Modeling environment .38Figure 11 - Relationship between FC-PI and mo
47、deling rise times .39Figure 12 - Basic “Black Box“ with four single ended ports or two differential ports .45Figure 13 - Single ended S-parameter matrix form 45Figure 14 - A single conductor example .46Figure 15 - A two conductor example 46Figure 16 - A three region example 47Figure 17 - General con
48、figuration for an 11 conductor PCB 48Figure 18 - Maxwell matrices for the 11 conductor example .49Figure 19 - I/V simulation example 67Figure 20 - Ramp data simulation example 70Figure 21 - IBIS pulldown I/V example .77Copyright American National Standards Institute Provided by IHS under license wit
49、h ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Table of ContentsTable 1 - Parameter class examples for validation 41Table 2 - Numerical properties for the 11 conductor example 48Table 3 - Recommended load circuits and waveforms for V/s data extraction.71Table 4 - IBIS file header information.73Table 5 - IBIS file revision levels73Table 6 - I
