1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.d
2、la.mil/ Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, LINEAR-DIGITAL, PRESSURE SENSOR SIGNAL CONDITIONER, MONOLITHIC SILICON 13-07-01 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13619 REV PAGE 1 OF 17 AMSC N/A 5962-V066-13 Provided by IHSNot f
3、or ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13619 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance pressure sensor signal conditioner mic
4、rocircuit, with an operating temperature range of -40C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation:
5、 V62/13619 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 PGA400-EP Pressure sensor signal conditioner 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Numb
6、er of pins JEDEC PUB 95 Package style X 36 JEDEC MO-220 Plastic quad flatpack no-lead 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E G
7、old flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13619 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Power supply voltage, (VDDContinuous) . -5.5 V
8、to 16.0 V Voltage at VP_OTP . -0.3 V to 8.0 V Voltage at sensor input and drive pins -0.3 V to 3.6 V Voltage at any IO pin except at VOUT1/OWI -0.3 V to VDD+ 0.3 V Voltage at VOUT1/OWI pin -0.3 V to 7.5 V Supply current, (IDD, Short on VOUT1 or VOUT2) . -45 mA to +45 mA Output current, (Iout1, Iout2
9、) . -30 mA to +30 mA Minimum ESD Human Body Model (HBM) 2 kV Field induced Charge Device Model (CDM) . 500 V Maximum junction Temperature, (Tjmax) 150C Storage temperature, (Tstg) . -40C to 150C 1.4 Thermal characteristics. Thermal metric Case outline X Units Junction to ambient thermal resistance,
10、JA2/ 30.6 C/W Junction to case (top) thermal resistance, JCtop3/ 16.4 Junction to board thermal resistance, JB4/ 5.4 Junction to top characterization parameter, JT5/ 0.2 Junction to board characterization parameter, JB6/ 5.4 Junction to case (bottom) thermal resistance, JCbot7/ 0.7 1/ Stresses beyon
11、d those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximu
12、m rated conditions for extended periods may affect device reliability. 2/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K-board, as specified in JESD51-7, in an environment described in JESD51-2a. 3/ The junction to case (to
13、p) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 4/ The junction to board thermal resistance is obtained by simulating in an environment with a ring c
14、old plate fixture to control the PCB temperature, as described in JESD51-8. 5/ The junction to top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sec
15、tions 6 and 7). 6/ The junction to board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 7/ The junction to case (bottom) thermal r
16、esistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND
17、 AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13619 REV PAGE 4 1.5 Recommended operating conditions. Power supply voltage, (VDD) 4.5 V to 5.5 V Maximum power supply current, (IDD): Normal mode, VDD= 5 V, No load on VBRG, No load on DAC1 and DAC2 . 13.6 mA Low power mode, VDD=
18、5 V, No load on VBRG, No load on DAC1 and DAC2, AFE turned OFF . 9.5 mA OTP programming voltage, (VP_OTP) 7.0 V to 7.8 V Maximum OTP programming current, (I_VP_OTP) . 3 mA Minimum OTP programming timing per byte, (tprog_OTP) . 120 s Operating ambient temperature, (TA) . -40C to 125C Programming temp
19、erature, (OTP or EEPROM) -40C to 140C Maximum micro start-up time, (VDD ramp rate 1V/s) 250 s 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51 Methodology for the Thermal Measurement of Component Packages
20、 (Single Semiconductor Device). JESD51-2a Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-8 Integrated Circuits Thermal Test Method Environment Conditions Ju
21、nction-to-board (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD ANSI SEMI STANDARD G30-88 null Test Method for
22、 Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org)
23、3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked
24、with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimens
25、ion. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13619 REV PAGE 5 3.5.1 Case out
26、line. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Truth table. The truth table shall be as shown in figure 4. 3.5.5 Fu
27、nctional block diagram. The functional block diagram shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13619 REV PAGE 6 TABLE I. Electrical perf
28、ormance characteristics. 1/ Test Symbol Test conditions Limits Unit Min TYP Max Over voltage protection Over voltage protection threshold OV 5.5 6.1 7.0 V Over voltage protection hysteresis OVhyst410 mV Regulators AVDD voltage VAVDDCAVDD= 100 nF 3.3 V AVDD current I_AVDD VAVDD= 3.3 V 5 mA DVDD volta
29、ge VDVDDNo EEPROM programming 3.3 V EEPROM programming 3.6 INTERNAL OSCILLATOR AND EXTERNAL CRYSTAL INTERFACE Internal Oscillator Internal Oscillator frequency Tamb = 25C 38.4 40 41.6 MHz Internal Oscillator frequency Across operating temperature 36.3 43.7 External 40 MHz crystal Low level input vol
30、tage on XTAL -0.3 0.1 x VDDV High level input voltage on XTAL 0.7 x VDDVDD+ 0.3 SENSOR SUPPLY VBRG supply for resistive bridge sensors Supply voltage VBRG0.44 k RBRG 20 k 3.2 3.33 3.4 V Resistive Bridge Resistance RBRG0.44 20 k Capacitive load CBRGRBRG= 20 k 500 pF Line regulation VDD= 4.5 V, 5.5 V,
31、 RBRG= 0.44 k -40 40 mV Load regulation VDD= 5.0 V, 10 A ILOAD 10 mA -40 40 mV See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13619 REV PAGE 7
32、 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions Limits Unit Min TYP Max SENSOR SUPPLY Continued. ICAPx supply for capacitive sensors Supply current amplitude on ICAP, TA= 25C ICAP_A CI2:0 = 000, ICAP_V = 100 mV -5.3 -4.3 A CI2:0 = 001, ICAP_V = 100 mV -8
33、-6.6 CI2:0 = 010, ICAP_V = 100 mV -10.8 -8.8 CI2:0 = 011, ICAP_V = 100 mV -13.5 -11.1 CI2:0 = 100, ICAP_V = 100 mV -16.2 -13.3 CI2:0 = 101, ICAP_V = 100 mV -18.9 -15.5 CI2:0 = 110, ICAP_V = 100 mV -21.6 -17.8 CI2:0 = 111, ICAP_V = 100 mV -24.4 -20.1 CI2:0 = 000, ICAP_V = 3.2 V 4.5 5.6 CI2:0 = 001, I
34、CAP_V = 3.2 V 6.9 8.5 CI2:0 = 010, ICAP_V = 3.2 V 9.2 11.3 CI2:0 = 011, ICAP_V = 3.2 V 11.5 14.1 CI2:0 = 100, ICAP_V = 3.2 V 13.6 16.7 CI2:0 = 101, ICAP_V = 3.2 V 15.8 19.2 CI2:0 = 110, ICAP_V = 3.2 V 18.1 22.1 CI2:0 = 111, ICAP_V = 3.2 V 20.4 24.8 Variation over temperature -5.0 +5.0 % Capacitive s
35、ensor drive Voltage at CPx and CRx pin CPx_V, CRx_V CV1:0 = 00 70 90 110 mV CV1:0 = 01 255 300 345 CV1:0 = 10 425 500 575 CV1:0 = 11 595 700 805 Self oscillating current mode demodulator for capacitive sensors Gain in transimpedance amplifier RF/ RREFCR1:0 = 00, RREF= 78 k -1.07 -1.01 -0.94 V/V CR1:
36、0 = 01, RREF= 78 k -2.13 -1.97 -1.82 CR1:0 = 10, RREF= 78 k -4.24 -3.93 -3.63 CR1:0 = 11, RREF= 78 k -8.45 -7.85 -7.26 Feedback capacitor in Transimpedance amplifier Cf 14 16 18 pF TEMPERATURE SENSOR Temperature range -55 125 C Temperature ADC resolution 10 bits Temperature ADC update rate 8 ms Gain
37、 2/ 2.7 2.8 2.9 LSB/C Offset 2/ -105 -66 LSB Total error -4 4 C See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13619 REV PAGE 8 TABLE I. Elect
38、rical performance characteristics - Continued. 1/ Test Symbol Test conditions Limits Unit Min TYP Max ANALOG FRONT ENDS Stage 1 Gain for resistive bridge sensors Gain steps Sx_G12:0 = 000 3.0 V/V Sx_G12:0 = 001 4.4 Sx_G12:0 = 010 6.8 Sx_G12:0 = 011 10.2 Sx_G12:0 = 100 14.6 Sx_G12:0 = 101 25.5 Sx_G12
39、:0 = 110 34.0 Sx_G12:0 = 111 51.0 Band width -3 dB, Gain = 111 7 KHz Stage 2 Gain Gain steps Sx_G24:0 = 00000 0.97 1.01 1.05 V/V Sx_G24:0 = 00001 1.06 1.11 1.16 Sx_G24:0 = 00010 1.18 1.23 1.28 Sx_G24:0 = 00011 1.31 1.37 1.42 Sx_G24:0 = 00100 1.45 1.52 1.58 Sx_G24:0 = 00101 1.61 1.68 1.76 Sx_G24:0 =
40、00110 1.79 1.87 1.94 Sx_G24:0 = 00111 1.98 2.07 2.16 Sx_G24:0 = 01000 2.20 2.29 2.39 Sx_G24:0 = 01001 2.44 2.55 2.65 Sx_G24:0 = 01010 2.71 2.83 2.94 Sx_G24:0 = 01011 3.00 3.13 3.26 Sx_G24:0 = 01100 3.34 3.48 3.62 Sx_G24:0 = 01101 3.74 3.90 4.06 Sx_G24:0 = 01110 4.12 4.30 4.48 Sx_G24:0 = 01111 4.61 4
41、.81 5.01 Sx_G24:0 = 10000 5.09 5.31 5.54 Sx_G24:0 = 10001 5.67 5.92 6.16 Sx_G24:0 = 10010 6.26 6.52 6.79 Sx_G24:0 = 10011 6.93 7.23 7.53 Sx_G24:0 = 10100 7.70 8.04 8.37 Sx_G24:0 = 10101 8.57 8.95 9.32 Sx_G24:0 = 10110 9.54 9.96 10.37 Sx_G24:0 = 10111 10.62 11.06 11.51 Sx_G24:0 = 11000 11.76 12.27 12
42、.79 Sx_G24:0 = 11001 13.02 13.58 14.15 Sx_G24:0 = 11010 14.48 15.10 15.72 Sx_G24:0 = 11011 16.03 16.71 17.40 Sx_G24:0 = 11100 17.72 18.53 19.34 Sx_G24:0 = 11101 19.61 20.49 21.37 Sx_G24:0 = 11110 21.72 22.70 23.68 Sx_G24:0 = 11111 23.85 25.06 26.28 Bandwidth -3dB, Gain setting = 11111 120 KHz See fo
43、otnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13619 REV PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test con
44、ditions Limits Unit Min TYP Max Offset and offset TC compensation Offset compensation low Offset setting = 0x000, Stage 1 Gain setting = 0b000 -385 -324 -279 mV Offset compensation high Offset setting = 0x3FF, Stage 1 Gain setting = 0b000 279 324 385 mV Offset compensation resolution Stage 1 gain se
45、tting = 0b000 0.59 0.72 mV/step Offset TC compensation low Offset TC setting = 0x00, Stage 1 Gain value = 0b000 -371 V/C Offset TC compensation high Offset TC setting = 0x3F, Stage 1 Gain value = 0b000 361 V/C Offset TC compensation resolution Stage 1 gain value = 0b000 11.6 V/V/C/step Reference tem
46、perature 22 C ANALOG TO DIGITAL CONVERTER ADC Buffer for 16 bit AD converter 1 Gain 1.9 2 2.1 V/V DC level shift ADC_BUF bit = 1 -1.74 -1.65 -1.55 V DC offset -15 15 mV ADC Buffer for 10 bit AD converter 2 VIN3 Input voltage range 0.425 1.7 V Gain 1.09 1.15 1.21 V/V DC offset -15 15 mV VIN3 voltage
47、versus ADC code Gain 3/ 740 760 780 LSB/V Offset 3/ -850 -820 -790 LSB Gain temperature coefficient Tamb= 25C 0.02 LSB/V/C Offset temperature coefficient Tamb= 25C -0.02 LSB/C Integral nonlinearity -1 1 LSB One wire interface Communication Baud rate 2400 115000 Bits per second OWI enable OWI_EN 6.5 7.0 V OWI enable hysteresis OWI_ENhys50 mV Internal pullup 10 k Activation signal pulse low time 12 ms Activation signal pulse high time 12 ms OWI transceiver RX threshold OWI_VIH 0.7 x VDDVDD+ 0.3 V OWI transceiver RX thr
