1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Make correction to vendor part number. - TVN 03-02-06 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 09-02-17 Charles F. Saffle Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV B B B B B B B B
2、B B B B B B REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thanh V. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Thanh V. Nguyen APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, ANALOG MUL
3、TIPLEXER/DEMULTIPLEXER, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03606 YY-MM-DD 02-12-18 REV B PAGE 1 OF 14 AMSC N/A 5962-V039-09 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE
4、A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance analog multiplexer/demultiplexer microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number.
5、The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03606 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device
6、 type(s). Device type Generic Circuit function 01 74HC4051-EP Analog multiplexer/demultiplexer 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MS-012 Plastic small-outline package 1.2.3 Lead finishes. The lead finishes
7、 are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-
8、,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC VEE) -0.5 V to 10.5 V 2/ Supply voltage range (VCC) . -0.5 V to 7.0 V Supply voltage range (VEE) +0.5 V to -7.0 V Input clamp current
9、 (IIK) (VI -0.5 V or VI VCC+ 0.5 V) . 20 mA Output clamp current (IOK) (VO VEE 0.5 V or VO VCC+ 0.5 V). 20 mA Switch current (VI VEE 0.5 V or VI VCC+ 0.5 V). 25 mA Continuous current through VCCor GND. 50 mA VEEcurrent (IEE). -20 mA Storage temperature range (TSTG). -65C to 150C Maximum junction tem
10、perature (TJ) 150C Lead temperature (during soldering): At distance 1/16 1/32 inch (1.59 0.79 mm) from case for 10 s max. 300C Package thermal impedance (JA): 3/ X package . 73C/W 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range (VCC) . 2.0 V to 6.0 V 6/ Supply voltage range (VCC- VE
11、E) (See figure 1) 2.0 V to 10.0 V Supply voltage range (VEE) (See figure 1). 0.0 V to -6.0 V 6/ Input control voltage range (VI) . 0.0 V to VCC Analog switch I/O voltage range (VIS) VEEto VCCMinimum high level input voltage (VIH): VCC= 2.0 V 1.5 V VCC= 4.5 V 3.15 V VCC= 6.0 V 4.20 V Maximum low leve
12、l input voltage (VIL): VCC= 2.0 V 0.5 V VCC= 4.5 V 1.35 V VCC= 6.0 V 1.80 V Minimum input transition rise or fall time (tt): VCC= 2.0 V, 4.5 V, and 6.0 V 0.0 ns Maximum input transition rise or fall time (tt): VCC= 2.0 V 1000 ns VCC= 4.5 V 500 ns VCC= 6.0 V 400 ns Operating free-air temperature rang
13、e (TA). -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is no
14、t implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage referenced to GND unless otherwise specified. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. 4/ Use of this product beyond the manufacturers desig
15、n rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ In certain applications, t
16、he external load resistor current may include both VCCand signal-line components. To avoid drawing VCCcurrent when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6 V (calculated from rONvalues shown in table I, herein). No V
17、CCcurrent flows through RLif the switch current flows into the COM OUT/IN A terminal. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 4 FIGURE 1.
18、Recommended operating area as a function of supply voltages. 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addresse
19、d to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE
20、code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical
21、performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 2.
22、 3.5.2 Truth table. The truth table shall be as shown in figure 3. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 5. 3.5.5 Test circuits and timing waveforms. The tests circuits and timing wavefor
23、ms shall be as shown in figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Limits Tes
24、t Symbol Conditions VEE VCC Temperature, TA Device type Min Max Unit 25C 160 0.0 V 4.5 V -55C to 125C 240 25C 140 0.0 V 6.0 V -55C to 125C 210 25C 120 VIS= VCCor VEE IO= 1 mA VI= VIHor VIL2/ See figure 7 -4.5 V 4.5 V -55C to 125C 180 25C 180 0.0 V 4.5 V -55C to 125C 270 25C 160 0.0 V 6.0 V -55C to 1
25、25C 240 25C 130 ON resistance rON VIS= VCCto VEE IO= 1 mA VI= VIHor VIL2/ See figure 7 -4.5 V 4.5 V -55C to 125C All 195 0.0 V 4.5 V 10 typical 0.0 V 6.0 V 8.5 typical Maximum ON resistance rON Between any two channels -4.5 V 4.5 V 25C All 5 typical 25C 0.2 0.0 V 6.0 V -55C to 125C 2.0 25C 0.4 Switc
26、h ON/OFF leakage current IIZ For switch OFF: When VIS= VCC, VOS= VEE; When VIS= VEE, VOS= VCCFor switch ON: All applicable combinations of VISand VOSvoltage levels VI= VIHor VIL2/ -5.0 V 5.0 V -55C to 125C All 4.0 A 25C All 0.1 Control input leakage current IIL VI= VCCor GND 0.0 V 6.0 V -55C to 125C
27、 1.0 A See footnotes ant end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 6 TABLE I. Electrical performance characteristics - Continu
28、ed. 1/ Limits Test Symbol Conditions VEE VCC Temperature, TA Device type Min Max Unit 25C 8 VI = VCC or GND IO= 0 A When VIS= VEE, VOS= VCC0.0 V 6.0 V -55C to 125C 160 25C All 16 Quiescent supply current ICC VI= VCCor GND IO= 0 A When VIS= VCC, VOS= VEE-5.0 V 5.0 V -55C to 125C 320 A Input control c
29、apacitanceCICL= 50 pF 25C, -55C to 125C All 10 pF Power dissipation capacitance CPD3/ tr= tf= 6 ns 5.0 V 25C All 50 typical pF CL= 15 pF See figure 6 5.0 V 25C 4 25C 60 0.0 V 2.0 V -55C to 125C 90 25C 12 0.0 V 4.5 V -55C to 125C 18 25C 10 0.0 V 6.0 V -55C to 125C 15 25C 8 Propagation delay time, swi
30、tch IN to OUT tpdCL= 50 pF See figure 6 -4.5 V 4.5 V -55C to 125C All 12 ns CL= 15 pF See figure 6 5.0 V 25C 19 25C 225 0.0 V 2.0 V -55C to 125C 340 25C 45 0.0 V 4.5 V -55C to 125C 68 25C 38 0.0 V 6.0 V -55C to 125C 57 25C 32 Propagation delay time, switch turn “ON” delay from S or E to switch outpu
31、t tenCL= 50 pF See figure 6 -4.5 V 4.5 V -55C to 125C All 48 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 7 T
32、ABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Conditions VEE VCC Temperature, TA Device type Min Max Unit CL= 15 pF See figure 6 5.0 V 25C 19 25C 225 0.0 V 2.0 V -55C to 125C 340 25C 45 0.0 V 4.5 V -55C to 125C 68 25C 38 0.0 V 6.0 V -55C to 125C 57 25C 32 Propagat
33、ion delay time, switch turn “OFF” delay from S or E to switch output tdisCL= 50 pF See figure 6 -4.5 V 4.5 V -55C to 125C All 48 ns Analog channel characteristics Switch input capacitance CIN 25C All 5 typical pF Common output capacitance CCOM 25C All 25 typical pF -2.25 V 2.25 V 145 typical Minimum
34、 switch frequency response at 3 dB fMAX4/ 5/ See figures 6 and 7 -4.5 V 4.5 V 25C All 180 typical MHz -2.25 V 2.25 V 0.035 typical Sine-wave distortion See figure 6 -4.5 V 4.5 V 25C All 0.018 typical % -2.25 V 2.25 V TBD S or E to switch feed-through noise 5/ 6/ See figure 6 -4.5 V 4.5 V 25C All TBD
35、 mV -2.25 V 2.25 V -73 typical Switch “OFF” signal feed-through 5/ 6/ See figures 6 and 7 -4.5 V 4.5 V 25C All -75 typical dB 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not ne
36、cessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ The values to be used for VIHand VILshall be the VIHminimum and VILmaximum value
37、s listed in section 1.4 herein. 3/ CPDis used to determine the dynamic power consumption, per package. PD= CPDVCC2fI+ (CL+ CS) VCC2fOWhere fOis output frequency; fIis input frequency; CLis output load capacitance; CSis switch capacitance; and VCCis supply voltage. 4/ Adjust input voltage to obtain 0
38、 dBm at VOSfor fIN= 1 MHz. 5/ VISis centered at (VCCVEE)/2. 6/ Adjust input for 0 dBm. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 8 Case X Di
39、mensions Inches Millimeters Inches Millimeters Symbol Min Max Min Max Symbol Min Max Min Max A .069 1.75 E .150 .157 3.81 4.00 A1 .004 .010 0.10 0.25 E1 .228 .244 5.80 6.20 b .014 .020 0.35 0.51 e .050 BSC 1.27 BSC c .008 NOM 0.20 NOM L .016 .044 0.40 1.12 D .386 .394 9.80 10.00 NOTES: 1. All linear
40、 dimensions are in inches (millimeters). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed .006 inches. 4. Fall within JEDEC MS-012. FIGURE 2. Case outline. Provided by IHSNot for ResaleNo reproduction or networking pe
41、rmitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 9 Inputs E S2 S1 S0 ON channel(s) L L L L A0 L L L H A1 L L H L A2 L L H H A3 L H L L A4 L H L H A5 L H H L A6 L H H H A7 H X X X None H = High voltage level L
42、 = Low voltage level X = Dont care FIGURE 3. Truth table. FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 10 Device type
43、01 Case outlines: X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 CHANNEL I/O A4 9 ADDRESS SEL S2 2 CHANNEL I/O A6 10 ADDRESS SEL S1 3 COM OUT/IN A 11 ADDRESS SEL S0 4 CHANNEL I/O A7 12 CHANNEL I/O A3 5 CHANNEL I/O A5 13 CHANNEL I/O A0 6 E 14 CHANNEL I/O A1 7 VEE 15 CHANNEL
44、 I/O A2 8 GND 16 VCC FIGURE 5. Terminal connections. FIGURE 6. Test circuits and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE
45、 11 FIGURE 6. Test circuits and timing waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03606 REV B PAGE 12 NOTES: 1. CLincludes probe and te
46、st-fixture capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. Phase relationships
47、 between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 , tr= 6 ns, tf= 6 ns. 4. For clock inputs, fmaxis measured with the input duty cycle at 50%. 5. The outputs are measured one at a time with one input transition per measurement. 6. tPLZand tPHZare the same as tdis; tPZLand tPZHare the same as ten; tPLHand tPHLare the same as tpd. FIGURE 6. Test circuits and timing waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-
