DLA SMD-5962-00509 REV B-2013 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR MULTIPLEXER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf

上传人:eastlab115 文档编号:698174 上传时间:2019-01-02 格式:PDF 页数:17 大小:179.79KB
下载 相关 举报
DLA SMD-5962-00509 REV B-2013 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR MULTIPLEXER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf_第1页
第1页 / 共17页
DLA SMD-5962-00509 REV B-2013 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR MULTIPLEXER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf_第2页
第2页 / 共17页
DLA SMD-5962-00509 REV B-2013 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR MULTIPLEXER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf_第3页
第3页 / 共17页
DLA SMD-5962-00509 REV B-2013 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR MULTIPLEXER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf_第4页
第4页 / 共17页
DLA SMD-5962-00509 REV B-2013 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR MULTIPLEXER WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf_第5页
第5页 / 共17页
点击查看更多>>
资源描述

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. LTG 07-10-24 Thomas M. Hess B Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 13-01-25 Thomas M. Hess REV SHEET REV B B SHEET 15 16 REV STATUS REV B B B B B B B B B

2、B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFEN

3、SE AMSC N/A CHECKED BY Charles F. Saffle, Jr. APPROVED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 00-12-07 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-00509 SHEET

4、1 OF 16 DSCC FORM 2233 APR 97 5962-E214-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00509 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Sco

5、pe. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radia

6、tion Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 00509 01 Q E A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see

7、 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as fo

8、llows: Device type Generic number Circuit function 01 54LVC257A Quadruple 2-line to 1-line data selector/multiplexer with three-state outputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirem

9、ents documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 F

10、lat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00509 DLA L

11、AND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +6.5 V dc DC input voltage range (VIN) -0.5 V dc to +6.5 V dc 4/ DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc 4/ 5/

12、Input clamp current (IIK) (VINVCC) . -50 mA Continuous output current (IO) . 50 mA Continuous current through VCCor GND . 100 mA Maximum power dissipation at TA= +55C (in still air) (PD) . 550 mW 6/ Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Therm

13、al resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +150C 1.4 Recommended operating conditions. 2/ 3/ 7/ Supply voltage range (VCC): Operating . +2.0 V dc to +3.6 V dc Data retention only . +1.5 V dc Minimum high level input voltage (VIH): VCC= 2.7 V to 3.6 V . +2.0 V M

14、aximum low level input voltage (VIL): VCC= 2.7 V to 3.6 V +0.8 V Input voltage range (VIN) +0.0 V dc to 5.5 V dc Output voltage range (VOUT). +0.0 V dc to VCCMaximum high level output current (IOH): VCC= 2.7 V -12 mA VCC= 3.0 V -24 mA Maximum low level output current (IOL): VCC= 2.7 V +12 mA VCC= 3.

15、0 V +24 mA Input transition rise or fall rate (t/V):. 0.0 to 10.0 ns/V Case operating temperature range (TC) . -55C to +125C _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliabili

16、ty. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ The input and output negative-voltage ratings may be exceeded provided that the input and

17、output clamp-current ratings are observed. 5/ The value of VCCis provided in the recommended operating conditions table. 6/ The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. 7/ Unused inputs must be held at VCCor GND to ens

18、ure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00509 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Go

19、vernment specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFI

20、CATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standar

21、d Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In th

22、e event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The i

23、ndividual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design,

24、construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections

25、 shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Ground bounce load circuit and waveforms. The ground bounce load circuit and waveforms shall be as specified on fi

26、gure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirrad

27、iation parameter limits are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00509 DLA LAND AND MARITIME COLUMBUS, OHIO 4

28、3218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 he

29、rein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still b

30、e marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificat

31、e of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that th

32、e manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Pr

33、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00509 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test and MIL

34、-STD-883 test method 1/ Symbol Test conditions 2/ -55C TC +125C +2.0 V VCC +3.6 V unless otherwise specified VCCGroup A subgroups Limits 3/ Unit Min Max High level output voltage 3006 VOHFor all inputs affecting output under test VIN= VIHor VILFor all other inputs VIN= VCCor GND IOH= -100 A 2.7 V an

35、d 3.6 V 1, 2, 3 VCC-0.2 V IOH= -12 mA 2.7 V 1, 2, 3 2.2 3.0 V 2.4 IOH= -24 mA 3.0 V 1, 2, 3 2.2 Low level output voltage 3007 VOLFor all inputs affecting output under test VIN= VIHor VILFor all other inputs VIN= VCCor GND IOL= +100 A 2.7 V and 3.6 V 1, 2, 3 0.2 V IOL= +12 mA 2.7 V 1, 2, 3 0.4 IOL= +

36、24 mA 3.0 V 1, 2, 3 0.55 Input current high 3010 IIHFor input under test, VIN= 5.5 V 3.6 V 1, 2, 3 +5.0 A Input current low 3009 IILFor input under test, VIN= GND 3.6 V 1, 2, 3 -5.0 A Three-state output leakage current high 3021 IOZH4/ VIN= VCCor GND VOUT= 3.6 V 3.6 V 1, 2, 3 15.0 A Three-state outp

37、ut leakage current low 3020 IOZL4/ VIN= VCCor GND VOUT= 0.0 V 3.6 V 1, 2, 3 -15.0 A Quiescent supply current 3005 ICCFor all inputs, VIN= VCCor GND IOUT= 0 A 3.6 V 1, 2, 3 10.0 A Quiescent supply current delta TTL input levels 3005 ICCFor input under test, VIN= VCC-0.6 V For all other inputs at VIN=

38、 VCCor GND 2.7 V and 3.6 V 1, 2, 3 500.0 A Input capacitance 3012 CINTC= +25C VIN= VCCor GND See 4.4.1c 3.3 V 4 8.0 pF Output capacitance 3012 COUTTC= +25C VIN= VCCor GND See 4.4.1c 3.3 V 4 10.0 pF Power dissipation capacitance CPD5/ See 4.4.1c TC= +25C f = 10 MHz 3.3 V 4 20.0 pF See footnotes at en

39、d of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00509 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics

40、 - Continued. Test and MIL-STD-883 test method 1/ Symbol Test conditions 2/ -55C TC +125C +2.0 V VCC +3.6 V unless otherwise specified VCCGroup A subgroups Limits 3/ Unit Min Max Functional test 3014 6/ VIN= VIHor VILVerify output VOSee 4.4.1b 2.0 V, 2.7 V and 3.6 V 7, 8 L H Low level ground bounce

41、noise VOLP7/ VIH= 2.7 V, VIL= 0.0 V TC= +25C See 4.4.1d See figure 4 3.0 V 4 1000 mV VOLV7/ 3.0 V 4 -700 High level VCCbounce noise VOHP7/ 3.0 V 4 850 VOHV7/ 3.0 V 4 -950 Propagation delay time, mA or mB to mY 3003 tPHL1, tPLH18/ CL= 50 pF minimum RL= 500 See figure 5 2.7 V 9,10,11 5.4 ns 3.0 V and

42、3.6 V 1.0 4.6 Propagation delay time, A/B to mY 3003 tPHL2, tPLH28/ 2.7 V 9,10,11 7.5 3.0 V and 3.6 V 1.0 6.4 Propagation delay time, output enable, OE to mY 3003 tPZH, tPZL8/ 2.7 V 9,10,11 6.7 3.0 V and 3.6 V 1.0 5.6 Propagation delay time, output disable, OE to mY 3003 tPHZ, tPLZ8/ 2.7 V 9,10,11 4

43、.7 ns 3.0 V and 3.6 V 0.5 4.3 1/ For tests not listed in the referenced MIL-STD-883, utilize the general test procedure of 883 under the conditions listed herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I here

44、in. Output terminals not designated shall be high level logic, low level logic, or open, except for the ICCtest, where the output terminals shall be open. When performing the ICCtest, the current meter shall be placed in the circuit such that all current flows through the meter. The values to be use

45、d for VIHand VILshall be the VIHminimum and VILmaximum values listed in section 1.4 herein. 3/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitu

46、de, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. 4/ Three-state output conditions are required. 5/ Power dissipation capacitance (CPD) determines both the power consumption (PD) and current consumption (IS). Where: PD= (CPD+ CL) (VCCx VCC)f + (ICCx VCC)

47、IS= (CPD+ CL) VCCf + ICCf is the frequency of the input signal; and CLis the external output load capacitance. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-00509 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-

48、3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. 6/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. Functional tests shall

展开阅读全文
相关资源
猜你喜欢
相关搜索

当前位置:首页 > 标准规范 > 国际标准 > 其他

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1