DLA SMD-5962-03236 REV C-2008 MICROCIRCUIT MEMORY DIGITAL CMOS 128K x 32-BIT (4M) RADIATION-HARDENED SRAM MONOLITHIC SILICON《128K x 32-BIT(4M)CMOS单片硅耐辐射数字静态存储器微电路》.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Editorial correction to Table I, IDD1 and IDD2 test blocks and test block for Table IIB. ksr 03-10-20 Raymond Monnin B Changed the dose rate from 3 rads(Si)/s to 1 rads(Si)/s in section 1.5 for Maximum total dose available condition. Boilerplate

2、paragraphs updated. ksr 04-11-08 Raymond Monnin C Section 1.3, changed supply voltage range high end (VDD1) to 2.1V. Added new footnote 4/ in section 1.4 and renumbered footnotes in section 1.5. Made significant change to max value in Table I for Operating supply current IDD1and Supply current stand

3、by IDD1. New footnote 6/ also added to Supply current standby, other footnotes renumbered. ksr 08-04-02 Robert M. Heber REV SHEET REV C C C C C C C C C C C C C SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMI

4、C N/A PREPARED BY Kenneth Rice STANDARD MICROCIRCUIT DRAWING CHECKED BY Raj Pithadia DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPRO

5、VAL DATE 03 09 12 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 128K x 32-BIT (4M), RADIATION-HARDENED SRAM, MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-03236 SHEET 1 OF 27 DSCC FORM 2233 APR 97 5962-E238-08 Provided by IHSNot for ResaleNo reproduction or networking permitted wit

6、hout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-03236 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assurance class levels consisting of high reliability (device cla

7、sses Q and M), space application (device class V), and for appropriate satellite and similar applications (device class T). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (R

8、HA) levels are reflected in the PIN. For device class T, the user is encouraged to review the manufacturers Quality Management (QM) plan as part of their evaluation of these parts and their acceptability in the intended application. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R

9、 03236 01 Q X C Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q, T and V RHA marked devices shall meet the MIL-PRF-38535 sp

10、ecified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall i

11、dentify the circuit function as follows: Device type Generic number 1/ Circuit function Access time 01 8R128K32 128K X 32-bit Radiation-hardened SRAM (MIL Temp) 15 ns 02 8R128K32 128K X 32-bit Radiation-hardened SRAM (Extended Temp) 15 ns 1.2.3 Device class designator. The device class designator sh

12、all be a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q, V Certification and

13、 qualification to MIL-PRF-38535 T Certification and qualification to MIL-PRF-38535 with performance as specified in the device manufacturers approved quality management plan 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive d

14、esignator Terminals Package style X See figure 1 68 Ceramic quad Flat-pack 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38535 for classes Q, T and V or MIL-PRF-38535, appendix A for device class M. _ 1/ Generic numbers are also listed on the Standard Microcircuit Drawing Sourc

15、e Approval Bulletin at the end of this document and will also be listed in QML-38535 and MIL-HDBK-103. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-03236 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218

16、-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range, (VDD1) -0.3 V dc to +2.1 V dc Supply voltage range, (VDD2) -0.3 V dc to +3.8 V dc Voltage range on any input pin -0.3 V dc to +3.8 V dc Voltage range on any output pin -0.3 V dc to +3.8 V d

17、c Input current, dc. + 5 mA Power dissipation. 1.2 W Operating free-air temperature range, (TA) (Device 01) . -55C to +125C Operating free-air temperature range, (TA) (Device 02) . -40C to +125C Storage temperature range, (TSTG) -65C to +150C Junction temperature, (TJ) . +150C Thermal resistance, ju

18、nction-to-case, (JC): Case U . +5C/W 1.4 Recommended operating conditions. Supply voltage range, (VDD1) +1.7 V dc to +1.9 V dc 4/ Supply voltage range, (VDD2) 3.0 V dc to +3.6 V dc Supply voltage, (VSS) . 0 V dc Input voltage, dc. 0 V dc to VDD2Operating free-air temperature, (TA) (Device 01) . -55C

19、 to +125C Operating free-air temperature, (TA) (Device 02) . -40C to +125C 1.5 Radiation features Maximum total dose available (dose rate = 1 rads(Si)/s) . 30.0x 104rads(Si) Dose rate upset. 5/ Dose rate survivability . 5/ Single event phenomenon (SEP) effective linear energy threshold (LET) with no

20、 upsets 5/ with no latch-up . 100 MeV-cm2/mg 5/ Neutron irradiation. 3.0E14 n/cm22. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specifie

21、d, the issues of these documents are those listed in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Inter

22、face Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMDs). MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.dap

23、s.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.

24、 3/ All voltage values in this drawing are with respect to VSS. 4/ For increase noise immunity, supply voltage (VDD1) can be increased to 2.0 V. The parameters in Table I, (Electrical performance characteristics) are guaranteed through characterization at VDD1= 2.0 V dc. 5/ Contact the device manufa

25、cturer for detailed lot information. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-03236 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Gover

26、nment publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Sta

27、ndard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.or

28、g.) ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are no

29、rmally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the

30、text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q, T and V shall be in accordance with MIL-PR

31、F-38535, and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not effect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, ap

32、pendix A and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q, T and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). Th

33、e case outline(s) shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Data retention and Output load circuit. The output load c

34、ircuit shall be as specified on figure 4. 3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5. 3.2.6 Radiation test circuit. The radiation test circuit shall be as specified on figure 6. 3.2.7 Functional tests. Various functional tests used to test this device are containe

35、d in appendix A. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and shall

36、be made available to the preparing or acquiring activity upon request. For device classes Q, T and V, alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquirin

37、g activity upon request. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table I and shall apply over the full ambient operating t

38、emperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-03236 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 3.4 Electrical test requirements

39、. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking

40、of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q, T, and V shall be in accordance with MIL-PRF-385

41、35. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q, T and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in M

42、IL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q, T and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall

43、be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device

44、 classes Q, T and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q, T and V in MIL-PRF-38535 or for device class M in MIL-PRF-

45、38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that af

46、fects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of

47、the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 41 (see MIL-PRF-38535, appendix A). 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures sh

48、all be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan including screening (4.2), qualification (4.3), and conformance inspection (4.4). The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class T, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 and the device manufacturers QM plan, including screening, qualification, and conformance inspection. The performance envelope

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