1、JEDEC STANDARD Board Level Drop Test Method of Components for Handheld Electronic Products JESD22-B111A (Revision of JESD22-B111, July 2003) NOVEMBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved
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9、 Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 22-B111A -i- Test Method B111A (Revision of Test Method B111) TEST METHOD B111A BOARD LEVEL DROP TEST METH
10、OD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS Introduction The handheld electronic products fit into the consumer and portable market segments. Included in the handheld electronic products are cameras, calculators, cell phones, pagers, palm size PCs, Personal Computer Memory Card International A
11、ssociation (PCMCIA) cards, smart cards, mobile phones, personal digital assistants (PDAs) and other electronic products that can be conveniently stored in a pocket and used while held in users hand. These handheld electronic products are more prone to being dropped during their useful service life b
12、ecause of their size and weight. This dropping event can not only cause mechanical failures in the housing of the device but also create electrical failures in the printed circuit board (PCB) assemblies mounted inside the housing due to transfer of energy through PCB supports. The electrical failure
13、s may result from various failure modes such as cracking of circuit board, trace cracking on the board, cracking of solder interconnections between the components and the board, and the component cracks. The primary driver of these failures is excessive flexing of circuit board due to input accelera
14、tion to the board created from dropping the handheld electronic product. This flexing of the board causes relative motion between the board and the components mounted on it, resulting in component, interconnects, or board failures. This type of failure is a strong function of the combination of the
15、board design, construction, material, thickness, and surface finish; interconnect material and standoff height; and component size. JEDEC Standard No. 22-B111A Test Method B111A -ii- (Revision of Test Method B111) JEDEC Standard No. 22-B111A Page 1 Test Method B111A (Revision of Test Method B111) TE
16、ST METHOD B111A BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS (From JEDEC Board Ballot JCB-16-57, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope The board level drop test method is intended to evalu
17、ate and compare drop performance of surface mount electronic components for handheld electronic product applications in an accelerated test environment, where excessive flexure of a circuit board causes product failure. The purpose of this document is to standardize the test board and test methodolo
18、gy to provide a reproducible assessment of the drop test performance of surface mounted components while duplicating the failure modes normally observed during product level test. This is not meant to replace any system level drop test that maybe needed to qualify a specific handheld electronic prod
19、uct nor to cover the drop test required to simulate shipping and handling related shock of electronic components or PCB assemblies. These requirements are already addressed in JESD22-B110. The method is applicable to both area-array and perimeter-leaded surface mounted packages. The correlation betw
20、een test and field conditions is not yet fully established. Consequently, the test procedure is presently more appropriate for relative component performance comparison than for use as a pass/fail criterion. Rather, results should be used to augment existing data or establish baseline for potential
21、investigative efforts in package/board technologies. The comparability between different test sites, data acquisition methods, and board manufacturers has not been fully demonstrated by existing data. As a result, if the data are to be used for direct comparison of component performance, matching st
22、udy must first be performed to prove that the data are in fact comparable across different test sites and test conditions. This method is not intended to substitute for full characterization testing, which might incorporate substantially larger sample sizes and increased number of drops. Due to limi
23、ted sample size and number of drops specified here, it is possible that enough failure data may not be generated in every case to perform full statistical analysis. 2 Apparatus The shock-testing apparatus shall be capable of providing shock pulses with a peak acceleration of up to 2900 multiples of
24、gravity (g), a velocity change of 100 to 544 centimeters per second (39 to 214 inches per second), and a pulse duration between 0.3 and 8.0 milliseconds to the body of the component. For free-state testing, a velocity change of 125 to 544 centimeters per second (49 to 214 inches per second) and a pu
25、lse duration between 0.3 and 2.0 milliseconds is sufficient. Conversely, for mounted-state testing, apparatus capable of a velocity change of 100 to 544 centimeters per second (39 to 214 inches per second) and a pulse duration between 5.0 and 8.0 milliseconds to the body of the component is sufficie
26、nt. JEDEC Standard No. 22-B111A Page 2 Test Method B111A (Revision of Test Method B111) 2 Apparatus (contd) The acceleration pulse shall be a half-sine waveform with an allowable deviation from specified peak acceleration not greater than 10%. The test velocity change shall be 10% of the specified l
27、evel. The pulse duration shall be measured between the points at 10% of the peak acceleration during rise time and 10% of the peak acceleration during decay time. Absolute tolerances of the pulse duration shall be 15% of the specified duration. The test equipment transducer shall have a natural freq
28、uency greater than 5 times the frequency of the shock pulse being established, and measured through a low-pass filter having a bandwidth greater than 5 times the frequency of the shock pulse being established. Filtering should not be used in lieu of good measurement setup and procedure practices. Ap
29、propriate equipment calibration should be considered prior to any testing to ensure conformance to the specified targets and acceptable tolerances. Reserving a set of known good units is recommended for pre-test calibration exercise whenever new samples are to be tested. If calibration tests are con
30、ducted regularly, then following periodical preventive maintenance should suffice for the equipment to meet the target and tolerance limits. 3 Terms and definitions For purposes of this standard, the following definitions shall apply. component: A packaged semiconductor device. double-sided PCB asse
31、mbly: A printed circuit board assembly with components mounted on both sides of the board. event: An electrical discontinuity of resistance greater than 1000 ohms lasting for 1 microsecond or longer. event detector: A continuity test instrument capable of detecting electrical discontinuity of resist
32、ance greater than 1000 ohms lasting for 1 microsecond or longer. handheld electronic product: An electronic product that can conveniently be stored in a pocket (of sufficient size) and operated when held in users hand. Included in handheld electronic products are cameras, calculators, cell phones, p
33、agers, palm-size PCs (formerly called pocket organizers), Personal Computer Memory Card International Association (PCMCIA) cards, smart cards, mobile phones, personal digital assistants (PDAs), and other communication devices. peak acceleration: The maximum acceleration during the dynamic motion of
34、the test apparatus. pulse duration, acceleration interval: The time interval between the instant when the acceleration first reaches 10% of its specified peak level and the instant when the acceleration first returns to 10% of the specified peak level after having reached that peak level. single-sid
35、ed PCB assembly: A printed circuit board assembly with components mounted on only one side of the board. JEDEC Standard No. 22-B111A Page 3 Test Method B111A (Revision of Test Method B111) 3 Terms and definitions (contd) table drop height: The free-fall drop height of the drop table needed to attain
36、 the prescribed peak acceleration and pulse duration. change of velocity: the integration of acceleration with the time duration, i.e, the enclosed area of acceleration pulse with the time duration. effective change of velocity: the integration of acceleration with the pulse duration. The accelerati
37、on below 10% of the peak acceleration and any rebounces after the acceleration dropping to 10% of the peak value shall be ignored in the calculation. 4 Applicable documents JESD22-B110, Subassembly Mechanical Shock IPC-SMT-782, Surface Mount Design and Land Pattern Standard IPC-A-600, Acceptability
38、of Printed Boards J-STD-020, Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices J-STD-033, Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices IPC-9701A, Performance Test Methods and Qualification Requirements
39、 for Surface Mount Solder Attachments JESD94, Application Specific Qualification Using Knowledge Based Test Methodology IPC-JEDEC9706, Mechanical Shock In-situ Electrical Metrology Test Guidelines for FCBGA SMT Component Solder Crack and Pad Crater/Trace Crack Detection. 5 Test components and board
40、5.1 Components This standard covers all area arrays and perimeter-leaded surface-mountable packaged semiconductor devices such as BGAs, LGAs, CSPs, TSOPs, and QFNs typically used in handheld electronic product. The maximum size of the component body covered in this standard is 15 mm x 15 mm in gener
41、al. A larger body size may be used for a special board layout as described in detail in section 5.2. All components used for this testing must be daisy-chained. The daisy chain should either be done at the die level or by providing daisy chain links at the lead-frame or substrate level. In case of n
42、on-daisy chain die, a mechanical dummy die must be used inside the package to simulate the actual structure of the package. The die size and thickness should be similar to the functional die size to be used in application. The component materials, dimensions, and assembly processes shall be represen
43、tative of typical production device. JEDEC Standard No. 22-B111A Page 4 Test Method B111A (Revision of Test Method B111) 5.2 Test board Since the drop test performance is a function of the component and test board used for evaluation, this standard defines a preferred test board construction, dimens
44、ions, and materials that are representative of those used in handheld electronic products. If another board construction/material better represents a specific application, the test board construction, dimensions and materials should be documented. The test data generated using such a board shall be
45、correlated at least once by generating the same data on same component using the preferred board defined in this document. 5.2.1 Preferred board construction, materials, and design The preferred test board shall use build-up multilayer technology incorporating microvias using 2+6+2 stack-up. This is
46、 required as typical PCB assemblies used in handheld electronic systems are constructed using high density, buildup technology. The test board shall have a nominal thickness of 1.0 mm. A thinner board (0.8mm) may also be used but the drop test performance may be different and the correlation between
47、 different board thicknesses needs to be established. Table 1 provides the thickness, copper coverage, and the material for each layer for references only. The dielectric materials shall meet the mechanical properties requirements as given in Table 2. The PCB shall have Organic Solderability Preserv
48、atives (OSP) as surface finish to avoid any copper oxidation before component mounting. The glass transition temperature, Tg (DSC), of each dielectric material as well as of the composite board shall be 130 oC or greater. The modulus and Tg of the dielectric materials shall be specified. The boards
49、shall be symmetric in construction about the mid-plane of the board, except for the minor differences in the top and bottom two layers. Since a typical product board may have a combination of microvia in pad and no via in pad for area array packages for routing purposes, it is required that such components (BGAs, CSPs, etc.).) be tested on board with both microvia and non-microvia PCB pads. This shall be accomplished by designing double-sided boards with mirror component footprint on each side (top and bottom) of the board. The board Side A may have microvias in pads (“via in pad”)
